MPC8343VRADDB datasheet(62/79 Pages) FREESCALE

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MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 10

Freescale Semiconductor

Clocking

As described in Section 19, “Clocking,” the LBIUCM, DDRCM, and SPMF parameters in the reset

configuration word low and the CFG_CLKIN_DIV configuration input signal select the ratio between the

primary clock input (CLKIN or PCI_CLK) and the internal coherent system bus clock (csb_clk). Table 55

and Table 56 show the expected frequency values for the CSB frequency for select csb_clk to

CLKIN/PCI_SYNC_IN ratios.

1011

× 11

1100

× 12

1101

× 13

1110

× 14

1111

× 15

Table 55. CSB Frequency Options for Host Mode

CFG_CLKIN_DIV

at Reset1

SPMF

csb_clk :

Input Clock Ratio2

Input Clock Frequency (MHz)2

16.67

33.33

66.67

csb_clk Frequency (MHz)

Low

0010

2 : 1

133

Low

0011

3 : 1

100

200

Low

0100

4 : 1

100

133

266

Low

0101

5 : 1

125

166

333

Low

0110

6 : 1

100

150

200

Low

0111

7 : 1

116

175

233

Low

1000

8 : 1

133

200

266

Low

1001

9 : 1

150

225

300

Low

1010

10 : 1

166

250

333

Low

1011

11 : 1

183

275

Low

1100

12 : 1

200

300

Low

1101

13 : 1

216

325

Low

1110

14 : 1

233

Low

1111

15 : 1

250

Low

0000

16 : 1

266

Table 54. System PLL Multiplication Factors (continued)

RCWL[SPMF]

System PLL Multiplication Factor

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