MPC8343VRADDB datasheet(23/79 Pages) FREESCALE

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MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 10

Freescale Semiconductor

Ethernet: Three-Speed Ethernet, MII Management

8.2

MII, RGMII, and RTBI AC Timing Specifications

The AC timing specifications for MII, RGMII, and RTBI are presented in this section.

8.2.1

MII AC Timing Specifications

This section describes the MII transmit and receive AC timing specifications.

8.2.1.1

MII Transmit AC Timing Specifications

Table 25 provides the MII transmit AC timing specifications.

Figure 8 shows the MII transmit AC timing diagram.

Figure 8. MII Transmit AC Timing Diagram

Table 25. MII Transmit AC Timing Specifications

At recommended operating conditions with LVDD/OVDD of 3.3 V ± 10%.

Parameter/Condition

Symbol1

Min

Typ

Max

Unit

TX_CLK clock period 10 Mbps

tMTX

—400

—

TX_CLK clock period 100 Mbps

tMTX

—40—

TX_CLK duty cycle

tMTXH/tMTX

—

TX_CLK to MII data TXD[3:0], TX_ER, TX_EN delay

tMTKHDX

TX_CLK data clock rise (20%–80%)

tMTXR

1.0

—

4.0

TX_CLK data clock fall (80%–20%)

tMTXF

1.0

—

4.0

Note:

1. The symbols for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for inputs

and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMTKHDX symbolizes MII transmit timing

(MT) for the time tMTX clock reference (K) going high (H) until data outputs (D) are invalid (X). In general, the clock reference

symbol is based on two to three letters representing the clock of a particular function. For example, the subscript of tMTX

represents the MII(M) transmit (TX) clock. For rise and fall times, the latter convention is used with the appropriate letter:

R (rise) or F (fall).

TX_CLK

TXD[3:0]

tMTKHDX

tMTX

tMTXH

tMTXR

tMTXF

TX_EN

TX_ER

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