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MPC8343VRADDB Datasheet(PDF) 24 Page - Freescale Semiconductor, Inc |
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MPC8343VRADDB Datasheet(HTML) 24 Page - Freescale Semiconductor, Inc |
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24 / 79 page ![]() MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 10 24 Freescale Semiconductor Ethernet: Three-Speed Ethernet, MII Management 8.2.1.2 MII Receive AC Timing Specifications Table 26 provides the MII receive AC timing specifications. Figure 9 provides the AC test load for TSEC. Figure 9. TSEC AC Test Load Figure 10 shows the MII receive AC timing diagram. Figure 10. MII Receive AC Timing Diagram Table 26. MII Receive AC Timing Specifications At recommended operating conditions with LVDD/OVDD of 3.3 V ± 10%. Parameter/Condition Symbol1 Min Typ Max Unit RX_CLK clock period 10 Mbps tMRX — 400 — ns RX_CLK clock period 100 Mbps tMRX —40— ns RX_CLK duty cycle tMRXH/tMRX 35 — 65 % RXD[3:0], RX_DV, RX_ER setup time to RX_CLK tMRDVKH 10.0 — — ns RXD[3:0], RX_DV, RX_ER hold time to RX_CLK tMRDXKH 10.0 — — ns RX_CLK clock rise (20%–80%) tMRXR 1.0 — 4.0 ns RX_CLK clock fall time (80%–20%) tMRXF 1.0 — 4.0 ns Note: 1. The symbols for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMRDVKH symbolizes MII receive timing (MR) with respect to the time data input signals (D) reach the valid state (V) relative to the tMRX clock reference (K) going to the high (H) state or setup time. Also, tMRDXKL symbolizes MII receive timing (GR) with respect to the time data input signals (D) went invalid (X) relative to the tMRX clock reference (K) going to the low (L) state or hold time. In general, the clock reference symbol is based on three letters representing the clock of a particular function. For example, the subscript of tMRX represents the MII (M) receive (RX) clock. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall). Output Z0 = 50 Ω OVDD/2 RL = 50 Ω RX_CLK RXD[3:0] tMRDXKH tMRX tMRXH tMRXR tMRXF RX_DV RX_ER tMRDVKH Valid Data |
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