M24LR64-R_1004 datasheet(56/126 Pages) STMICROELECTRONICS

Part #	M24LR64-R_1004

Description	64 Kbit EEPROM with password protection & dual interface: 400kHz I²C serial bus & ISO 18000-3 mode 1 RF protocol at 13.56MHz

PDF	126 Pages

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Manufacturer	STMICROELECTRONICS [STMicroelectronics]

Direct Link	http://www.st.com

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56 / 126 page

Data storage format identifier (DSFID)

M24LR64-R

56/126

Doc ID 15170 Rev 9

Data storage format identifier (DSFID)

The data storage format identifier indicates how the data is structured in the M24LR64-R

memory. The logical organization of data can be known instantly using the DSFID. It can be

programmed and locked using the Write DSFID and Lock DSFID commands.

15.1

CRC

The CRC used in the M24LR64-R is calculated as per the definition in ISO/IEC 13239. The

initial register contents are all ones: “FFFF”.

The two-byte CRC are appended to each request and response, within each frame, before

the EOF. The CRC is calculated on all the bytes after the SOF up to the CRC field.

Upon reception of a request from the VCD, the M24LR64-R verifies that the CRC value is

valid. If it is invalid, the M24LR64-R discards the frame and does not answer to the VCD.

Upon reception of a Response from the M24LR64-R, it is recommended that the VCD

verifies whether the CRC value is valid. If it is invalid, actions to be performed are left to the

discretion of the VCD designer.

The CRC is transmitted least significant byte first. Each byte is transmitted least significant

bit first.

Table 19.

CRC transmission rules

LSByte

MSByte

LSBit

MSBit

LSBit

MSBit

CRC 16 (8 bits)

M24LR64-R_1004 Datasheet(PDF) 56 Page - STMicroelectronics