ADRF6655ACPZ-R7 datasheet(21/44 Pages) AD

21 / 44 page

ADRF6655

Rev. 0 | Page 21 of 44

IP3SET LINEARIZATION FEATURE

The IP3SET pin (Pin 29) controls the overall current consumption

of the mixer core depending on the applied voltage. If left open,

the voltage on the IP3SET pin is ~2.3 V, and a typical input IP3 of

~25 dBm or higher can be expected across the operating frequency

range. As the IP3SET voltage is increased, the overall supply

current increases and the input IP3 can be improved from ~3 dB to

6 dB. For upconversion applications, an IP3SET voltage of ~3.2 V to

3.3 V results in very high output IP3 performance in excess of

30 dBm. Using an external resistor divider network connected

between VCC and GND, the IP3SET voltage can be derived.

Alternatively, the on-board 3.3 V LDO output (Pin 2) can be

used to derive the applied IP3SET voltage. However, it is

advisable to use good bypassing and a series inductor or ferrite

choke to ensure good high frequency isolation between Pin 1 and

Pin 29. If an auxiliary control DAC is available, the IP3SET pin can

be driven dynamically in applications where power levels are

changing over time, and it is desirable to conserve power at

lower input signal levels. Figure 62 and Figure 63 illustrate the

output linearity dependency on the IP3SET voltage. Note that

gain is independent of the IP3SET voltage.

2.3 2.4 2.5 2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7

IP3SET (V)

OUTPUT FREQUENCY = 1210MHz

OUTPUT FREQUENCY = 1500MHz

Figure 62. Output IP3 vs. IP3SET Voltage for Output Frequency

OUTPUT FREQUENCY (MHz)

–10

–8

–6

–4

–2

2.3 2.4 2.5 2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7

OUTPUT FREQUENCY = 1210 MHz

OUTPUT FREQUENCY = 1500 MHz

OUTPUT P1dB

GAIN

Figure 63. Output P1dB and Gain vs. IP3SET Voltage

CDAC LINEARIZATION FEATURE

In addition to the IP3SET broadband linearization solution, the

ADRF6655 also includes a special linearizer designed to provide

enhanced IP3 performance at higher input frequencies. At low

input frequencies, the CDAC setting offers very little influence

on input IP3, and a CDAC setting of 15 is usually recommended.

At high input frequencies, the CDAC setting can boost input

IP3 as much as 5 dB with essentially no increase in supplied

power. At a given input frequency, the ADRF6655 offers an

optimum CDAC setting to provide high input IP3 performance.

The recommended optimum CDAC setting vs. RF input frequency

is shown in Figure 64.

1840

1940

2040

2140

2240

2340

2440

RF FREQUENCY (MHz)

BEST CDAC AT 25°C

INTERCEPT

BEST CDAC AT 85°C

Figure 64. Optimum CDAC Setting for Downconversion vs. RF Input Frequency

EXTERNAL LO INTERFACE

The ADRF6655 provides the option to use an external signal

source for the LO into the mixer. It is important to note that the

applied LO signal is divided by 2 or divided by 3 prior to the

actual mixer core within the ADRF6655. The divider is determined

by the register settings in LO path and mixer control register,

(see the Register 5—LO Path and Mixer Control section). The

LO input pins (Pin 37 and Pin 38) present a broadband balanced

50 Ω input interface similar to the input pins (Pin 25 and Pin 26).

The LOP and LON input pins should be dc blocked and driven

from a balanced 50 Ω source. When not in use, the LOP and

LON pins may be left unconnected.

ADRF6655ACPZ-R7 Datasheet(PDF) 21 Page - Analog Devices

ADRF6655ACPZ-R7 Datasheet(HTML) 21 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44

Datasheet Download

Link URL