ADRF6655ACPZ-R7 datasheet(19/44 Pages) AD

19 / 44 page

ADRF6655

Rev. 0 | Page 19 of 44

ANALOG INTERFACES

The basic circuit connections for a typical ADRF6655 application

are presented in Figure 52.

SUPPLY CONNECTIONS

The ADRF6655 has several supply connections and on-board

regulated reference voltages that should be bypassed to ground

using low inductance bypass capacitors located in close proximity

to the supply and reference pins of the ADRF6655. Specifically

Pin 1, Pin 2, Pin 9, Pin 10, Pin 17, Pin 22, Pin 27, and Pin 40

should be bypassed to ground using individual bypass capacitors.

Pin 9 is the supply used for the on-board VCO, and for best

phase noise performance, several bypass capacitors ranging

from 100 pF to 10 μF may help to improve phase noise

performance. For additional details on bypassing the supply

nodes, refer to the evaluation board schematic in Figure 82.

SYNTHESIZER CONNECTIONS

The ADRF6655 includes an on-board VCO and PLL for LO

synthesis. An external reference must be applied for the PLL to

operate. The external reference should be ac-coupled and provide a

~1 V p-p nominal input level at Pin 6. The reference is compared

to an internally divided version of the VCO output frequency to

create a charge pump error current to control and lock the VCO. The

charge pump output current is filtered and converted to a VTUNE

control voltage through the external loop filter. ADIsimPLL™

can be a helpful tool when designing the external charge pump

loop filter. The typical Kv of the VCO, the charge pump output

current magnitude, and PFD frequency should all be considered

when designing the loop filter. The charge pump current magnitude

can be set internally or with an external RSET resistor connected

to Pin 5 and ground, along with the internal digital settings

applied to the PLL (see the Register 4—Charge Pump, PFD, and

Reference Path Control section for more details).

OUTPUT MATCHING AND BIASING

The ADRF6655 output stage consists of collector connected

output transistors with on-board pull-up resistors. The output

transistors and pull-up network presents a 200 Ω differential

output impedance in parallel with a small amount of shunt

capacitance. The measured RC equivalent impedance of Pin 18

and Pin 19 is ~250 Ω//1.5 pF. This impedance needs to be taken

into consideration when designing the external output matching

network. In addition to matching the presented output source

impedance to the intended load impedance, it is important to

provide pull-up choke connections to the supply pins to allow

for dc current to directly supply the mixer output transistors.

The reactance of the pull-up chokes may need to be considered

when designing the output matching network. For convenience,

several output matching/bias networks are presented in Figure 53

through Figure 58 for reference.

ADRF6655

850MHz OUTPUT INTERFACE

+VCC

1.5pF

GJM

15nH

0302CS

12nH

0302CS

12nH

0302CS

TC4-14G2+

2.7pF

GJM

1nF

IF OUT

Figure 53. 850 MHz Output Matching Network Using the Center-Tap of the

TC4-14T+ Transformer for Biasing the Open Collector Outputs (Output

return loss measured to be better than 12 dB from 800 MHz to 925 MHz.)

ADRF6655

900MHz OUTPUT INTERFACE

+VCC

1pF

GJM

68nH

0402CS

5.1nH

0402CS

47nH

0603CS

5.1nH

0402CS

+VCC

47nH

0603CS

TC1-1-13M+

1nF

150pF

1nF

IF OUT

150pF

Figure 54. 900 MHz Output Matching Network Using the TC1-1-13M+ 1:1

Impedance Ratio Balun and External Pull-Up Choke Inductors (Output return

loss measured to be better than 12 dB from 815 MHz to 1075 MHz.)

ADRF6655

1200MHz OUTPUT INTERFACE

+VCC

1.8pF

GJM

17nH

0302CS

2.1nH

0302CS

47nH

0603CS

2.1nH

+VCC

47nH

0603CS

TC1-1-13M+

IF OUT

1nF

150pF

1nF

150pF

Figure 55. 1200 MHz Output Matching Network (Output return loss

measured to be better than 12 dB from 950 MHz to 1500 MHz.)

ADRF6655

1300MHz OUTPUT INTERFACE

+VCC

1.2pF

GJM

10nH

0302CS

2.7nH

0402CS

47nH

0603CS

2.7nH

0402CS

+VCC

47nH

0603CS

TC1-1-13M+

IF OUT

1nF

150pF

1nF

150pF

Figure 56. 1300 MHz Output Matching Network (Output return loss

measured to be better than 12 dB from 1075 MHz to 1525 MHz.)

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