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XIO2000AI Datasheet(PDF) 68 Page - TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS |
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XIO2000AI Datasheet(HTML) 68 Page - TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS |
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68 / 159 page  Classic PCI Configuration Space 58 April 2007 Revised October 2008 SCPS155C 4.18 Memory Base Register This read/write register specifies the lower limit of the memory addresses that the bridge forwards downstream. See Table 4−9 for a complete description of the register contents. PCI register offset: 20h Register type: Read-only, Read/Write Default value: 0000h BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 4−9. Memory Base Register Description BIT FIELD NAME ACCESS DESCRIPTION 15:4 MEMBASE RW Memory base. Defines the lowest address of the memory address range that determines when to forward memory transactions from one interface to the other. These bits correspond to address bits [31:20] in the memory address. The lower 20 bits are assumed to be 00000h. 3:0 RSVD R Reserved. Returns 0h when read. 4.19 Memory Limit Register This read/write register specifies the upper limit of the memory addresses that the bridge forwards downstream. See Table 4−10 for a complete description of the register contents. PCI register offset: 22h Register type: Read-only, Read/Write Default value: 0000h BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 4−10. Memory Limit Register Description BIT FIELD NAME ACCESS DESCRIPTION 15:4 MEMLIMIT RW Memory limit. Defines the highest address of the memory address range that determines when to forward memory transactions from one interface to the other. These bits correspond to address bits [31:20] in the memory address. The lower 20 bits are assumed to be FFFFFh. 3:0 RSVD R Reserved. Returns 0h when read. 4.20 Prefetchable Memory Base Register This read/write register specifies the lower limit of the prefetchable memory addresses that the bridge forwards downstream. See Table 4−11 for a complete description of the register contents. PCI register offset: 24h Register type: Read-only, Read/Write Default value: 0001h BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Table 4−11. Prefetchable Memory Base Register Description BIT FIELD NAME ACCESS DESCRIPTION 15:4 PREBASE RW Prefetchable memory base. Defines the lowest address of the prefetchable memory address range that determines when to forward memory transactions from one interface to the other. These bits correspond to address bits [31:20] in the memory address. The lower 20 bits are assumed to be 00000h. The prefetchable base upper 32 bits register (offset 28h, see Section 4.22) specifies bits [63:32] of the 64-bit prefetchable memory address. 3:0 64BIT R 64-bit memory indicator. These read-only bits indicate that 64-bit addressing is supported for this memory window. |
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