XIO2000AI datasheet(65/159 Pages) TAOS

65 / 159 page

Classic PCI Configuration Space

April 2007 Revised October 2008

SCPS155C

4.12 Secondary Bus Number Register

This read/write register specifies the bus number of the PCI bus segment that the PCI interface is connected

to. The bridge uses this register to determine how to respond to a type 1 configuration transaction.

PCI register offset:

19h

Read/Write

Default value:

00h

BIT NUMBER

RESET STATE

4.13 Subordinate Bus Number Register

This read/write register specifies the bus number of the highest number PCI bus segment that is downstream

of the bridge. The bridge uses this register to determine how to respond to a type 1 configuration transaction.

PCI register offset:

1Ah

Read/Write

Default value:

00h

BIT NUMBER

RESET STATE

4.14 Secondary Latency Timer Register

This read/write register specifies the secondary bus latency timer for the bridge, in units of PCI clock cycles.

PCI register offset:

1Bh

Read/Write

Default value:

00h

BIT NUMBER

RESET STATE

4.15 I/O Base Register

This read/write register specifies the lower limit of the I/O addresses that the bridge forwards downstream.

See Table 4−6 for a complete description of the register contents.

PCI register offset:

1Ch

Read-only, Read/Write

Default value:

01h

BIT NUMBER

RESET STATE

Table 4−6. I/O Base Register Description

BIT

FIELD NAME

ACCESS

DESCRIPTION

7:4

IOBASE

I/O base. Defines the bottom address of the I/O address range that determines when to forward I/O

transactions from one interface to the other. These bits correspond to address bits [15:12] in the

I/O address. The lower 12 bits are assumed to be 000h. The 16 bits corresponding to address bits

[31:16] of the I/O address are defined in the I/O base upper 16 bits register (offset 30h, see

Section 4.24).

3:0

IOTYPE

I/O type. This field is read-only 1h indicating that the bridge supports 32-bit I/O addressing.

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