XIO2000AI datasheet(29/159 Pages) TAOS

29 / 159 page

Introduction

April 2007 Revised October 2008

SCPS155C

Table 2−9. Clock Terminals

SIGNAL

GZZ/ZZZ

BALL #

ZHC

BALL #

ZHH

BALL #

I/O

TYPE

CELL

TYPE

CLAMP

RAIL

EXTERNAL

PARTS

DESCRIPTION

REFCLK_SEL

A16

D11

A14

CMOS

VDD_33

Pullup or

pulldown

resistor

Reference clock select. This

terminal selects the reference

clock input.

0 = 100-MHz differential

common reference clock

used.

1 = 125-MHz single-ended,

reference clock used.

REFCLK+

C17

C14

C13

DIFF

VDD_33

−

Reference clock. REFCLK+ and

REFCLK− comprise the

differential input pair for the

100-MHz system reference

clock. For a single-ended,

125-MHz system reference

clock, use the REFCLK+ input.

REFCLK−

C16

B14

C14

DIFF

VDD_33

Capacitor to

VSS for

single-ended

mode

Reference clock. REFCLK+ and

REFCLK− comprise the

differential input pair for the

100-MHz system reference

clock. For a single-ended,

125-MHz system reference

clock, attach a capacitor from

REFCLK− to VSS.

CLK

P03

L03

PCI

Bus

VCCP

−

PCI clock input. This is the clock

input to the PCI bus core.

CLKOUT0

CLKOUT1

CLKOUT2

CLKOUT3

CLKOUT4

CLKOUT5

CLKOUT6

C08

B09

B10

A11

A12

A13

B14

D07

A08

A09

D09

A11

C10

C11

D07

B08

A09

D10

B10

B11

A13

PCI

Bus

VCCP

−

PCI clock outputs. These clock

outputs are used to clock the

PCI bus. If the bridge PCI bus

clock outputs are used, then

CLKOUT6 must be connected to

the CLK input.

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