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HD6432138SW Datasheet(PDF) 210 Page - Renesas Technology Corp |
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HD6432138SW Datasheet(HTML) 210 Page - Renesas Technology Corp |
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210 / 1061 page ![]() Section 6 Bus Controller Rev. 4.00 Jun 06, 2006 page 156 of 1004 REJ09B0301-0400 T1 Address bus φ RD Bus cycle A Data bus T2 T3 T1 T2 Bus cycle B Long output floating time Data collision (a) Idle cycle not inserted T1 φ RD T2 T3 TI T1 (b) Idle cycle inserted T2 WR WR Address bus Data bus Bus cycle A Bus cycle B Figure 6.9 Example of Idle Cycle Operation 6.6.2 Pin States in Idle Cycle Table 6.6 shows pin states in an idle cycle. Table 6.6 Pin States in Idle Cycle Pins Pin State A15 to A0, IOS Contents of next bus cycle D7 to D0 High impedance AS High RD High WR High |
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