HD6432138SW datasheet(209/1061 Pages) RENESAS

209 / 1061 page

Section 6 Bus Controller

Rev. 4.00 Jun 06, 2006 page 155 of 1004

REJ09B0301-0400

6.5.3

Wait Control

As with the basic bus interface, either program wait insertion or pin wait insertion using the

WAIT

pin can be used in the initial cycle (full access) of the burst ROM interface. See section 6.4.5, Wait

Control.

Wait states cannot be inserted in a burst cycle.

6.6

Idle Cycle

6.6.1

Operation

When the H8S/2138 Group or H8S/2134 Group chip accesses external space, it can insert a 1-state

idle cycle (T

I) between bus cycles when a write cycle occurs immediately after a read cycle. By

inserting an idle cycle it is possible, for example, to avoid data collisions between ROM, with a

long output floating time, and high-speed memory, I/O interfaces, and so on.

If an external write occurs after an external read while the ICIS0 bit in BCR is set to 1, an idle

cycle is inserted at the start of the write cycle. This is enabled in advanced mode and normal

mode.

Figure 6.9 shows an example of the operation in this case. In this example, bus cycle A is a read

cycle from ROM with a long output floating time, and bus cycle B is a CPU write cycle. In (a), an

idle cycle is not inserted, and a collision occurs in cycle B between the read data from ROM and

the CPU write data. In (b), an idle cycle is inserted, and a data collision is prevented.

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