HD6432138SW datasheet(162/1061 Pages) RENESAS

162 / 1061 page

Section 5 Interrupt Controller

Rev. 4.00 Jun 06, 2006 page 108 of 1004

REJ09B0301-0400

Bit n

IRQnF

Description

[Clearing conditions]

(Initial value)

• Cleared by reading IRQnF when set to 1, then writing 0 in IRQnF

• When interrupt exception handling is executed when low-level detection is set

(IRQnSCB = IRQnSCA = 0) and

IRQn input is high*

• When IRQn interrupt exception handling is executed when falling, rising, or both-

edge detection is set (IRQnSCB = 1 or IRQnSCA = 1)*

[Setting conditions]

• When IRQn input goes low when low-level detection is set (IRQnSCB = IRQnSCA =

• When a falling edge occurs in IRQn input when falling edge detection is set

(IRQnSCB = 0, IRQnSCA = 1)

• When a rising edge occurs in IRQn input when rising edge detection is set

(IRQnSCB = 1, IRQnSCA = 0)

• When a falling or rising edge occurs in IRQn input when both-edge detection is set

(IRQnSCB = IRQnSCA = 1)

(n = 7 to 0)

Note:

When a product, in which a DTC is incorporated, is used in the following settings, the

corresponding flag bit is not automatically cleared even when exception handling, which

is a clear condition, is executed and the bit is held at 1.

(1) When DTCEA3 is set to 1 (ADI is set to an interrupt source), IRQ4F flag is not

automatically cleared.

(2) When DTCEA2 is set to 1 (ICIA is set to an interrupt source), IRQ5F flag is not

automatically cleared.

(3) When DTCEA1 is set to 1 (ICIB is set to an interrupt source), IRQ6F flag is not

automatically cleared.

(4) When DTCEA0 is set to 1 (OCIA is set to an interrupt source), IRQ7F flag is not

automatically cleared.

When activation interrupt sources of DTC and IRQ interrupts are used with the above

combinations, clear the interrupt flag by software in the interrupt handling routine of the

corresponding IRQ.

HD6432138SW Datasheet(PDF) 162 Page - Renesas Technology Corp