HD6432138SW datasheet(166/1061 Pages) RENESAS

166 / 1061 page

Section 5 Interrupt Controller

Rev. 4.00 Jun 06, 2006 page 112 of 1004

REJ09B0301-0400

5.2.8

Break Address Registers A, B, C (BARA, BARB, BARC)

A23

R/W

A22

R/W

A21

R/W

A20

R/W

A19

R/W

A16

R/W

A18

R/W

A17

R/W

Bit

BARA

Initial value

Read/Write

A15

R/W

A14

R/W

A13

R/W

A12

R/W

A11

R/W

A10

R/W

Bit

BARB

Initial value

Read/Write

R/W

—

R/W

Bit

BARC

Initial value

Read/Write

BAR consists of three 8-bit readable/writable registers (BARA, BARB, and BARC), and is used to

specify the address at which an address break is to be executed.

Each of the BAR registers is initialized to H'00 by a reset and in hardware standby mode. They are

not initialized in software standby mode.

BARA Bits 7 to 0—Address 23 to 16 (A23 to A16)

BARB Bits 7 to 0—Address 15 to 8 (A15 to A8)

BARC Bits 7 to 1—Address 7 to 1 (A7 to A1)

These bits specify the address at which an address break is to be executed. BAR bits A15 to A1

are compared with internal address bus lines A15 to A1, respectively.

The address at which the first instruction byte is located should be specified as the break address.

Occurrence of the address break condition may not be recognized for other addresses.

In normal mode, no comparison is made with address lines A23 to A16.

BARC Bit 0—Reserved: This bit cannot be modified and is always read as 0.

HD6432138SW Datasheet(PDF) 166 Page - Renesas Technology Corp

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