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HD6432138SW Datasheet(PDF) 780 Page - Renesas Technology Corp |
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HD6432138SW Datasheet(HTML) 780 Page - Renesas Technology Corp |
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780 / 1061 page ![]() Section 25 Electrical Characteristics Rev. 4.00 Jun 06, 2006 page 726 of 1004 REJ09B0301-0400 Table 25.10 I 2C Bus Timing Conditions: V CC = 3.0 V to 5.5 V, VSS = 0 V, φ = 5 MHz to maximum operating frequency, T a = –20 to +75°C Ratings Item Symbol Min Typ Max Unit Test Conditions Notes SCL clock cycle time t SCL 12 —— t cyc Figure 25.26 SCL clock high pulse width t SCLH 3 —— t cyc SCL clock low pulse width t SCLL 5 —— t cyc SCL, SDA input rise time t Sr —— 7.5* t cyc SCL, SDA input fall time t Sf —— 300 ns SCL, SDA input spike pulse elimination time t SP —— 1t cyc SDA input bus free time t BUF 5 —— t cyc Start condition input hold time t STAH 3 —— t cyc Retransmission start condition input setup time t STAS 3 —— t cyc Stop condition input setup time t STOS 3 —— t cyc Data input setup time t SDAS 0.5 —— t cyc Data input hold time t SDAH 0 —— ns SCL, SDA capacitive load C b —— 400 pF Note: * 17.5t cyc can be set according to the clock selected for use by the I 2C module. For details, see section 16.4, Usage Notes. |
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