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HD6432138SW Datasheet(PDF) 779 Page - Renesas Technology Corp |
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HD6432138SW Datasheet(HTML) 779 Page - Renesas Technology Corp |
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779 / 1061 page  Section 25 Electrical Characteristics Rev. 4.00 Jun 06, 2006 page 725 of 1004 REJ09B0301-0400 Table 25.9 Timing of On-Chip Supporting Modules (2) Condition A: V CC = 5.0 V ±10%, VSS = 0 V, φ = 2 MHz to maximum operating frequency, T a = –20 to +75°C (regular specifications), T a = –40 to +85°C (wide-range specifications) Condition B: V CC = 4.0 V to 5.5 V, VSS = 0 V, φ = 2 MHz to maximum operating frequency, T a = –20 to +75°C (regular specifications), T a = –40 to +85°C (wide-range specifications) Condition C: V CC = 3.0 V to 5.5 V, VSS = 0 V, φ = 2 MHz to maximum operating frequency, T a = –20 to +75°C Condition A Condition B Condition C 20 MHz 16 MHz 10 MHz Item Symbol Min Max Min Max Min Max Unit Test Conditions CS/HA0 setup item t HAR 10 — 10 — 10 — ns Figure 25.25 HIF read cycle CS/HA0 hold time t HRA 10 — 10 — 10 — ns IOR pulse width t HRPW 120 — 120 — 220 — ns HDB delay time t HRD — 100 — 100 — 200 ns HDB hold time t HRF 025 0 25 0 40 ns HIRQ delay time t HIRQ — 120 — 120 — 200 ns CS/HA0 setup item t HAW 10 — 10 — 10 — ns HIF write cycle CS/HA0 hold time t HWA 10 — 10 — 10 — ns IOW pulse width t HWPW 60 — 60 — 100 — ns HDB setup time Fast A20 gate not used t HDW 30 — 30 — 50 — ns Fast A20 gate used 45 — 55 — 85 — ns HDB hold time t HWD 15 — 15 — 25 — ns GA20 delay time t HGA — 90 — 90 — 180 ns |
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