HD6432138SW datasheet(775/1061 Pages) RENESAS

775 / 1061 page

Section 25 Electrical Characteristics

Rev. 4.00 Jun 06, 2006 page 721 of 1004

REJ09B0301-0400

(3) Bus Timing

Table 25.8 shows the bus timing. Operation in external expansion mode is not guaranteed when

operating on the subclock (

φ = 32.768 kHz).

Table 25.8

Bus Timing

Condition A: V

CC = 5.0 V ±10%, VSS = 0 V, φ = 2 MHz to maximum operating frequency,

a = –20 to +75°C (regular specifications),

a = –40 to +85°C (wide-range specifications)

Condition B: V

CC = 4.0 V to 5.5 V, VSS = 0 V, φ = 2 MHz to maximum operating frequency,

a = –20 to +75°C (regular specifications),

a = –40 to +85°C (wide-range specifications)

Condition C: V

CC = 3.0 V to 5.5 V, VSS = 0 V, φ = 2 MHz to maximum operating frequency,

a = –20 to +75°C

Condition A

Condition B

Condition C

20 MHz

16 MHz

10 MHz

Item

Symbol Min

Max

Min

Max

Min

Max

Unit

Test

Conditions

Address

delay time

—

Address

setup time

0.5

cyc –15

—

0.5

cyc –20

—

0.5

cyc –30

—

Figure

25.10 to

figure

25.14

Address

hold time

0.5

cyc –10

—

0.5

cyc –15

—

0.5

cyc –20

—

CS delay

time (

IOS)

CSD

—

AS delay

time

ASD

—

RD delay

time 1

RSD1

—

RD delay

time 2

RSD2

—

Read data

setup time

RDS

—

Read data

hold time

RDH

—

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