HD6432138SW datasheet(778/1061 Pages) RENESAS

778 / 1061 page

Section 25 Electrical Characteristics

Rev. 4.00 Jun 06, 2006 page 724 of 1004

REJ09B0301-0400

Condition A

Condition B

Condition C

20 MHz

16 MHz

10 MHz

Item

Symbol

Min

Max

Min

Max

Min

Max

Unit

Test

Conditions

TMR

Timer output

delay time

TMOD

—

100

Figure 25.18

Timer reset input

setup time

TMRS

—

Figure 25.20

Timer clock input

setup time

TMCS

—

Figure 25.19

Single

edge

TMCWH

1.5

—

1.5

—

1.5

—

cyc

Timer

clock

pulse

width

Both

edges

TMCWL

2.5

—

2.5

—

2.5

—

PWM,

PWMX

Pulse output

delay time

PWOD

—

100

Figure 25.21

SCI

Asynchro-

nous

Scyc

—

cyc

Figure 25.22

Input

clock

cycle

Synchro-

nous

—

Input clock pulse

width

SCKW

0.4

0.6

0.4

0.6

0.4

0.6

Scyc

Input clock rise time

SCKr

—

1.5

—

1.5

—

1.5

cyc

Input clock fall time

SCKf

—

1.5

—

1.5

—

1.5

Transmit data delay

time (synchronous)

TXD

—

100

Figure 25.23

Receive data setup

time (synchronous)

RXS

—

100

—

Receive data

hold time

(synchronous)

RXH

—

100

—

A/D

converter

Trigger input setup

time

TRGS

—

Figure 25.24

Note:

Only supporting modules that can be used in subclock operation.

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