HD6432138SW datasheet(729/1061 Pages) RENESAS

729 / 1061 page

Section 23 Clock Pulse Generator

Rev. 4.00 Jun 06, 2006 page 675 of 1004

REJ09B0301-0400

Table 23.4

External Clock Input Conditions

CC = 2.7 to 5.5 V

CC = 5.0 V ±10%

Item

Symbol

Min

Max

Min

Max

Unit

Test Conditions

External clock

input low pulse

width

EXL

—

Figure 23.6

External clock

input high

pulse width

EXH

—

External clock

rise time

EXr

—

5ns

External clock

fall time

EXf

—

5ns

0.4

0.6

0.4

0.6

cyc

φ ≥ 5 MHz Figure 25.5

Clock low

pulse width

—

φ < 5 MHz

0.4

0.6

0.4

0.6

cyc

φ ≥ 5 MHz

Clock high

pulse width

—

φ < 5 MHz

tEXH

tEXL

tEXr

tEXf

VCC × 0.5

EXTAL

Figure 23.6 External Clock Input Timing

Table 23.5 shows the external clock output settling delay time, and figure 23.7 shows the external

clock output settling delay timing. The oscillator and duty adjustment circuit have a function for

adjusting the waveform of the external clock input at the EXTAL pin. When the prescribed clock

signal is input at the EXTAL pin, internal clock signal output is fixed after the elapse of the

external clock output settling delay time (t

DEXT). As the clock signal output is not fixed during the

DEXT period, the reset signal should be driven low to maintain the reset state.

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