HD6432138SW datasheet(731/1061 Pages) RENESAS

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Section 23 Clock Pulse Generator

Rev. 4.00 Jun 06, 2006 page 677 of 1004

REJ09B0301-0400

23.4

Duty Adjustment Circuit

When the oscillator frequency is 5 MHz or higher, the duty adjustment circuit adjusts the duty

cycle of the clock signal from the oscillator to generate the system clock (

φ).

23.5

Medium-Speed Clock Divider

The medium-speed clock divider divides the system clock to generate

φ/2, φ/4, φ/8, φ/16, and φ/32

clocks.

23.6

Bus Master Clock Selection Circuit

The bus master clock selection circuit selects the system clock (

φ) or one of the medium-speed

clocks (

φ/2, φ/4, φ/8, φ/16, or φ/32) to be supplied to the bus master, according to the settings of

bits SCK2 to SCK0 in SBYCR.

23.7

Subclock Input Circuit

The subclock input circuit controls the subclock input from the EXCL pin.

Inputting the Subclock: When a subclock is used, a 32.768-kHz external clock should be input

from the EXCL pin. In this case, clear bit P96DDR to 0 in P9DDR and set bit EXCLE to 1 in

LPWRCR.

The subclock input conditions are shown in table 23.6 and figure 23.8.

Table 23.6

Subclock Input Conditions

CC = 2.7 to 5.5 V

Item

Symbol

Min

Typ

Max

Unit

Test Conditions

Subclock input low

pulse width

EXCLL

—

15.26

—

µs

Figure 23.8

Subclock input high

pulse width

EXCLH

—

15.26

—

µs

Subclock input rise time

EXCLr

——

Subclock input fall time

EXCLf

——

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