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HD6432138SW Datasheet(PDF) 733 Page - Renesas Technology Corp |
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HD6432138SW Datasheet(HTML) 733 Page - Renesas Technology Corp |
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733 / 1061 page ![]() Section 23 Clock Pulse Generator Rev. 4.00 Jun 06, 2006 page 679 of 1004 REJ09B0301-0400 23.9 Clock Selection Circuit This circuit selects the system clock used in the MCU. The clock signal generated in the EXTAL/XTAL pin oscillator is selected as the system clock when MCU is returned from high-speed mode, medium-speed mode, sleep mode, reset state, or standby mode. In sub-active mode, sub-sleep mode, and watch mode, the sub-clock signal input from EXCL pin is selected as the system clock. In these modes, modules such as CPU, TMR0, TMR1, WDT0, WDT1, and I/O ports operate on the φ SUB clock. The count clock for each timer is a clock obtained by dividing the φ SUB clock. |
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