HD6432138SW datasheet(645/1061 Pages) RENESAS

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Section 21 ROM (Mask ROM Version, H8S/2138 F-ZTAT, H8S/2134 F-ZTAT, and H8S/2132 F-ZTAT)

Rev. 4.00 Jun 06, 2006 page 591 of 1004

REJ09B0301-0400

21.5.3

Erase Block Registers 1 and 2 (EBR1, EBR2)

Bit

543210

EBR1

——

————

EB9/—*

EB8/—*

Initial value

000000

Read/Write

——

————

R/W*

Bit

543210

EBR2

EB7

EB6

EB5

EB4

EB3

EB2

EB1

EB0

Initial value

000000

Read/Write

R/W*

R/W

Notes: 1. In normal mode, these bits cannot be modified and are always read as 0.

2. Bits EB8 and EB9 are not present in the 64-kbyte versions; These bits must not be set

to 1.

EBR1 and EBR2 are registers that specify the flash memory erase area block by block; bits 1 and

2 in EBR1 (128 kB versions only) and bits 7 to 0 in EBR2 are readable/writable bits. EBR1 and

EBR2 are each initialized to H'00 by a reset, in hardware standby mode, software standby mode,

subactive mode, subsleep mode, and watch mode, and the SWE bit in FLMCR1 is not set. When a

bit in EBR1 or EBR2 is set, the corresponding block can be erased. Other blocks are erase-

protected. Set only one bit in EBR1 or EBR2 (more than one bit cannot be set). When on-chip

flash memory is disabled, a read will return H'00, and writes are invalid.

The flash memory block configuration is shown in table 21.5.

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