HD6432138SW datasheet(647/1061 Pages) RENESAS

647 / 1061 page

Section 21 ROM (Mask ROM Version, H8S/2138 F-ZTAT, H8S/2134 F-ZTAT, and H8S/2132 F-ZTAT)

Rev. 4.00 Jun 06, 2006 page 593 of 1004

REJ09B0301-0400

Bit 3—Flash Memory Control Register Enable (FLSHE): Setting the FLSHE bit to 1 enables

read/write access to the flash memory control registers. If FLSHE is cleared to 0, the flash

memory control registers are deselected. In this case, the flash memory control register contents

are retained.

Bit 3

FLSHE

Description

Flash memory control registers deselected

(Initial value)

Flash memory control registers selected

Bit 2—Reserved: Do not write 1 to this bit.

Bits 1 and 0—Internal Clock Select 1 and 0 (ICKS1, ICKS0): These bits control 8-bit timer

operation. See section 12, 8-Bit Timers, for details.

21.6

On-Board Programming Modes

When pins are set to on-board programming mode, program/erase/verify operations can be

performed on the on-chip flash memory. There are two on-board programming modes: boot mode

and user program mode. The pin settings for transition to each of these modes are shown in table

21.6. For a diagram of the transitions to the various flash memory modes, see figure 21.3.

Only advanced mode setting is possible for boot mode.

In the case of user program mode, established in advanced mode or normal mode, depending on

the setting of the MD0 pin. In normal mode, only programming of a 56-kbyte area of flash

memory is possible.

Table 21.6

Setting On-Board Programming Modes

Mode

Mode Name

CPU Operating Mode

MD1

MD0

P92

P91

P90

Boot mode

Advanced mode

User program mode

Advanced mode

———

Normal mode

———

Note:

Can be used as I/O ports after boot mode is initiated.

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