HD6432138SW datasheet(643/1061 Pages) RENESAS

643 / 1061 page

Section 21 ROM (Mask ROM Version, H8S/2138 F-ZTAT, H8S/2134 F-ZTAT, and H8S/2132 F-ZTAT)

Rev. 4.00 Jun 06, 2006 page 589 of 1004

REJ09B0301-0400

Bit 0—Program (P): Selects program mode transition or clearing. Do not set the SWE, PSU,

ESU, EV, PV, or E bit at the same time.

Bit 0

Description

Program mode cleared

(Initial value)

Transition to program mode

[Setting condition]

When SWE = 1, and PSU = 1

21.5.2

Flash Memory Control Register 2 (FLMCR2)

Bit

543210

FLER

—

————

ESU

PSU

Initial value

000000

Read/Write

—

————

R/W

FLMCR2 is an 8-bit register that monitors the presence or absence of flash memory program/erase

protection (error protection) and performs setup for flash memory program/erase mode. FLMCR2

is initialized to H'00 by a reset, and in hardware standby mode. The ESU and PSU bits are cleared

to 0 in software standby mode, subactive mode, subsleep mode, and watch mode.

When on-chip flash memory is disabled, a read will return H'00, and writes are invalid.

Bit 7—Flash Memory Error (FLER): Indicates that an error has occurred during an operation on

flash memory (programming or erasing). When FLER is set to 1, flash memory goes to the error-

protection state.

HD6432138SW Datasheet(PDF) 643 Page - Renesas Technology Corp