HD6432138SW datasheet(641/1061 Pages) RENESAS

641 / 1061 page

Section 21 ROM (Mask ROM Version, H8S/2138 F-ZTAT, H8S/2134 F-ZTAT, and H8S/2132 F-ZTAT)

Rev. 4.00 Jun 06, 2006 page 587 of 1004

REJ09B0301-0400

21.5

21.5.1

Flash Memory Control Register 1 (FLMCR1)

Bit

543210

FWE

SWE

——

Initial value

000000

Read/Write

R/W

——

R/W

FLMCR1 is an 8-bit register used for flash memory operating mode control. Program-verify mode

or erase-verify mode is entered by setting SWE to 1. Program mode is entered by setting SWE to

1, then setting the PSU bit in FLMCR2, and finally setting the P bit. Erase mode is entered by

setting SWE to 1, then setting the ESU bit in FLMCR2, and finally setting the E bit. FLMCR1 is

initialized to H'80 by a reset, and in hardware standby mode, software standby mode, subactive

mode, subsleep mode, and watch mode. When on-chip flash memory is disabled, a read will return

H'00, and writes are invalid.

Writes to the EV and PV bits in FLMCR1 are enabled only when SWE=1; writes to the E bit only

when SWE = 1, and ESU = 1; and writes to the P bit only when SWE = 1, and PSU = 1.

Bit 7—Flash Write Enable (FWE): Controls programming and erasing of the on-chip flash

memory. This bit cannot be modified and is always read as 1.

Bit 6—Software Write Enable (SWE): Enables or disables flash memory programming. SWE

should be set before setting bits ESU, PSU, EV, PV, E, P, and EB9 to EB0, and should not be

cleared at the same time as these bits.

Bit 6

SWE

Description

Writes disabled

(Initial value)

Writes enabled

Bits 5 and 4—Reserved: These bits cannot be modified and are always read as 0.

HD6432138SW Datasheet(PDF) 641 Page - Renesas Technology Corp