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HD6432138SW Datasheet(PDF) 629 Page - Renesas Technology Corp |
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HD6432138SW Datasheet(HTML) 629 Page - Renesas Technology Corp |
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629 / 1061 page  Section 20 RAM Rev. 4.00 Jun 06, 2006 page 575 of 1004 REJ09B0301-0400 20.3 Operation 20.3.1 Expanded Mode (Modes 1, 2, and 3 (EXPE = 1)) When the RAME bit is set to 1, accesses to H8S/2138, H8S/2134, and H8S/2133 addresses H'(FF)E080 to H'(FF)EFFF and H'(FF)FF00 to H'(FF)FF7F, and H8S/2137, H8S/2132, and H8S/2130 addresses H'(FF)E880 to H'(FF)EFFF and H'(FF)FF00 to H'(FF)FF7F, are directed to the on-chip RAM. When the RAME bit is cleared to 0, accesses to addresses H'(FF)E080 to H'(FF)EFFF and H'(FF)FF00 to H'(FF)FF7F, are directed to the off-chip address space. Since the on-chip RAM is connected to the bus master by a 16-bit data bus, it can be written to and read in byte or word units. Each type of access is performed in one state. Even addresses use the upper 8 bits, and odd addresses use the lower 8 bits. Word data must start at an even address. 20.3.2 Single-Chip Mode (Modes 2 and 3 (EXPE = 0)) When the RAME bit is set to 1, accesses to H8S/2138, H8S/2134, and H8S/2133 addresses H'(FF)E080 to H'(FF)EFFF and H'(FF)FF00 to H'(FF)FF7F, and H8S/2137, H8S/2132, and H8S/2130 addresses H'(FF)E880 to H'(FF)EFFF and H'(FF)FF00 to H'(FF)FF7F, are directed to the on-chip RAM. When the RAME bit is cleared to 0, the on-chip RAM is not accessed. Undefined values are read from these bits, and writing is invalid. Since the on-chip RAM is connected to the bus master by a 16-bit data bus, it can be written to and read in byte or word units. Each type of access is performed in one state. Even addresses use the upper 8 bits, and odd addresses use the lower 8 bits. Word data must start at an even address. |
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