HD6432138SW datasheet(434/1061 Pages) RENESAS

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Section 14 Watchdog Timer (WDT)

Rev. 4.00 Jun 06, 2006 page 380 of 1004

REJ09B0301-0400

Bit 3—External Reset (XRST): Indicates the reset source. When the watchdog timer is used, a

reset can be generated by watchdog timer overflow in addition to external reset input. XRST is a

read-only bit. It is set to 1 by an external reset, and when the RST/

NMI bit is 1, is cleared to 0 by

an internal reset due to watchdog timer overflow.

Bit 3

XRST

Description

Reset is generated by watchdog timer overflow

Reset is generated by external reset input

(Initial value)

14.2.4

Notes on Register Access

The watchdog timer’s TCNT and TCSR registers differ from other registers in being more difficult

to write to. The procedures for writing to and reading these registers are given below.

Writing to TCNT and TCSR (Example of WDT0): These registers must be written to by a word

transfer instruction. They cannot be written to with byte transfer instructions.

Figure 14.2 shows the format of data written to TCNT and TCSR. TCNT and TCSR both have the

same write address. For a write to TCNT, the upper byte of the written word must contain H'5A

and the lower byte must contain the write data. For a write to TCSR, the upper byte of the written

word must contain H'A5 and the lower byte must contain the write data. This transfers the write

data from the lower byte to TCNT or TCSR.

TCNT write

TCSR write

Address: H'FFA8

H'5A

Write data

8 7

H'A5

Write data

8 7

Figure 14.2 Format of Data Written to TCNT and TCSR (Example of WDT0)

Reading TCNT and TCSR (Example of WDT0): These registers are read in the same way as

other registers. The read addresses are H'FFA8 for TCSR, and H'FFA9 for TCNT.

HD6432138SW Datasheet(PDF) 434 Page - Renesas Technology Corp