HD6432138SW datasheet(433/1061 Pages) RENESAS

Part #	HD6432138SW

Description	Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2100 Series

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Manufacturer	RENESAS [Renesas Technology Corp]

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Section 14 Watchdog Timer (WDT)

Rev. 4.00 Jun 06, 2006 page 379 of 1004

REJ09B0301-0400

• WDT1 input clock selection

Bit 4

Bit 2

Bit 1

Bit 0

Description

PSS

CKS2

CKS1

CKS0

Clock

Overflow Period* (when

φφφφ = 20 MHz

and

φφφφSUB = 32.768 kHz)

φ/2 (Initial value) 25.6 µs

φ/64

819.2 µs

φ/128

1.6 ms

φ/512

6.6 ms

φ/2048

26.2 ms

φ/8192

104.9 ms

φ/32768

419.4 ms

φ/131072

1.68 s

φSUB/2

15.6 ms

φSUB/4

31.3 ms

φSUB/8

62.5 ms

φSUB/16

125 ms

φSUB/32

250 ms

φSUB/64

500 ms

φSUB/128

1 s

φSUB/256

2 s

Note:

The overflow period is the time from when TCNT starts counting up from H'00 until

overflow occurs.

14.2.3

System Control Register (SYSCR)

CS2E

R/W

IOSE

R/W

INTM1

INTM0

R/W

XRST

RAME

R/W

NMIEG

R/W

HIE

R/W

Bit

Initial value

Read/Write

Only bit 3 is described here. For details on functions not related to the watchdog timer, see

sections 3.2.2 and 5.2.1, System Control Register (SYSCR), and the descriptions of the relevant

modules.

HD6432138SW Datasheet(PDF) 433 Page - Renesas Technology Corp

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