HD6432138SW datasheet(405/1061 Pages) RENESAS

405 / 1061 page

Section 13 Timer Connection [H8S/2138 Group]

Rev. 4.00 Jun 06, 2006 page 351 of 1004

REJ09B0301-0400

Bits 1 and 0—Clamp Waveform Mode Select 1 and 0 (CLMOD1, CLMOD0): These bits

select the signal source for the CLO signal (clamp waveform).

Bit 6

Bit 1

Bit 0

ISGENE

CLMOD1

CLMOD2

Description

The CL1 signal is selected

(Initial value)

The CL2 signal is selected

The CL3 signal is selected

The CL4 signal is selected

13.2.4

Edge Sense Register (SEDGR)

Bit

Initial value

Read/Write

Notes: 1. Only 0 can be written, to clear the flags.

2. The initial value is undefined since it depends on the pin states.

VEDG

R/(W)*

HEDG

R/(W)*

CEDG

R/(W)*

HFEDG

R/(W)*

VFEDG

R/(W)*

IVI

—*

PREQF

R/(W)*

IHI

—*

SEDGR is an 8-bit readable/writable register used to detect a rising edge on the timer connection

input pins and the occurrence of 2fH modification, and to determine the phase of the IVI and IHI

signals.

The upper 6 bits of SEDGR are initialized to 0 by a reset and in hardware standby mode. The

initial value of the lower 2 bits is undefined, since it depends on the pin states.

HD6432138SW Datasheet(PDF) 405 Page - Renesas Technology Corp

HD6432138SW Datasheet(HTML) 405 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL