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HD6432138SW Datasheet(PDF) 348 Page - Renesas Technology Corp |
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HD6432138SW Datasheet(HTML) 348 Page - Renesas Technology Corp |
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348 / 1061 page ![]() Section 11 16-Bit Free-Running Timer Rev. 4.00 Jun 06, 2006 page 294 of 1004 REJ09B0301-0400 11.3.7 Setting of FRC Overflow Flag (OVF) The FRC overflow flag (OVF) is set to 1 when FRC overflows (changes from H'FFFF to H'0000). Figure 11.13 shows the timing of this operation. H'FFFF H'0000 Overflow signal φ FRC OVF Figure 11.13 Setting of Overflow Flag (OVF) 11.3.8 Automatic Addition of OCRA and OCRAR/OCRAF When the OCRAMS bit in TOCR is set to 1, the contents of OCRAR and OCRAF are automatically added to OCRA alternately, and when an OCRA compare-match occurs a write to OCRA is performed. The OCRA write timing is shown in figure 11.14. OCRAR, F OCRA FRC φ A N N+A Compare-match signal N N+1 Figure 11.14 OCRA Automatic Addition Timing |
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