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HD6432138SW Datasheet(PDF) 347 Page - Renesas Technology Corp |
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HD6432138SW Datasheet(HTML) 347 Page - Renesas Technology Corp |
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347 / 1061 page  Section 11 16-Bit Free-Running Timer Rev. 4.00 Jun 06, 2006 page 293 of 1004 REJ09B0301-0400 11.3.6 Setting of Output Compare Flags A and B (OCFA, OCFB) The output compare flags are set to 1 by an internal compare-match signal generated when the FRC value matches the OCRA or OCRB value. This compare-match signal is generated at the last state in which the two values match, just before FRC increments to a new value. Accordingly, when the FRC and OCR values match, the compare-match signal is not generated until the next period of the clock source. Figure 11.12 shows the timing of the setting of OCFA and OCFB. OCRA or OCRB φ Compare-match signal FRC NN + 1 N OCFA or OCFB Figure 11.12 Setting of Output Compare Flag (OCFA, OCFB) |
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