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HD6432138SW Datasheet(PDF) 346 Page - Renesas Technology Corp |
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HD6432138SW Datasheet(HTML) 346 Page - Renesas Technology Corp |
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346 / 1061 page ![]() Section 11 16-Bit Free-Running Timer Rev. 4.00 Jun 06, 2006 page 292 of 1004 REJ09B0301-0400 11.3.5 Timing of Input Capture Flag (ICF) Setting The input capture flag ICFx (x = A, B, C, D) is set to 1 by the internal input capture signal. The FRC value is simultaneously transferred to the corresponding input capture register (ICRx). Figure 11.11 shows the timing of this operation. ICFA to ICFD φ FRC Input capture signal N N ICRA to ICRD Figure 11.11 Setting of Input Capture Flag (ICFA to ICFD) |
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