HD6432138SW datasheet(345/1061 Pages) RENESAS

Part #	HD6432138SW

Description	Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2100 Series

PDF	1061 Pages

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Manufacturer	RENESAS [Renesas Technology Corp]

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Section 11 16-Bit Free-Running Timer

Rev. 4.00 Jun 06, 2006 page 291 of 1004

REJ09B0301-0400

When ICRC or ICRD is used as a buffer register, its input capture flag is set by the selected

transition of its input capture signal. For example, if ICRC is used to buffer ICRA, when the edge

transition selected by the IEDGC bit occurs on the FTIC input capture line, ICFC will be set, and

if the ICIEC bit is set, an interrupt will be requested. The FRC value will not be transferred to

ICRC, however.

In buffered input capture, if the upper byte of either of the two registers to which data will be

transferred (ICRA and ICRC, or ICRB and ICRD) is being read when the input signal arrives,

input capture is delayed by one system clock (

φ) period. Figure 11.10 shows the timing when

BUFEA = 1.

Input capture

signal

FTIA

Read cycle:

CPU reads ICRA or ICRC

Figure 11.10 Buffered Input Capture Timing

(Input Capture Input When ICRA or ICRC Is Read)

HD6432138SW Datasheet(PDF) 345 Page - Renesas Technology Corp