TPLD2001DGSR datasheet(39/234 Pages) TI2

39 / 234 page

3-input user defined function, including the following standard digital logic functions (AND, NAND, OR, NOR,

XOR, XNOR).

When programmed for a LUT function, each macro-cell uses an 8-bit register to define the output function.

Table 8-8 shows truth tables for the 3-bit LUT.

Table 8-8. 3-bit LUT Truth Table

IN2

IN1

IN0

OUT

8.3.3.3.2 D Flip-Flop/Latch with Reset/Set

When used to implement a sequential logic element, the three input signals from the connection mux go to the

data (D), clock (CLK), and reset/set (nRST/nSET) inputs for the flip-flop or latch, with the output going back to

the connection mux. This macro-cell has user-configurable initial state, clock polarity, reset/set polarity, output

stage select, and output polarity parameters.

The operation of the D flip-flop/latch follows the functional descriptions below:

• The clock polarity is configurable and can be set to non-inverted (CLK) or inverted (nCLK).

– DFF with CLK: CLK is rising edge triggered, then Q = D; otherwise Q does not change.

– DFF with nCLK: CLK is falling edge triggered, then Q = D; otherwise Q does not change.

– Latch with CLK: when CLK is Low, then Q = D; otherwise Q remains the previous value (input D has no

effect on the output, when CLK is High).

– Latch with nCLK: when CLK is High, then Q = D; otherwise Q remains the previous value (input D has no

effect on the output, when CLK is Low).

• These DFF/Latches have an option for both an active-low and active-high reset/set:

– nRST: If High, then the DFF/Latch is in normal operation. If Low, then Q is reset to 0.

– RST: If Low, then the DFF/Latch is in normal operation. If High, then Q is reset to 0.

– nSET: If High, then the DFF/Latch is in normal operation. If Low, then Q is set to 1.

– SET: If Low, then the DFF/Latch is in normal operation. If High, then Q is set to 1.

• If reset/set is not desired, users can set the polarity to active-low and connect this input to VCC or a constant

High source.

• These DFF/Latches have the option to further isolate the output from the input with the use of a second

DFF/Latch and sampling on the falling edge of CLK and enabling the "Dual Stage DFF" option.

• The output polarity is configurable and can be set to non-inverted (Q) or inverted (nQ).

Table 8-9 and Table 8-10 show the truth tables for the D flip-flop and D latch with an active-low reset/set,

respectively.

www.ti.com

TPLD2001

SCPS286A – JULY 2025 – REVISED FEBRUARY 2026

Submit Document Feedback

Product Folder Links: TPLD2001

TPLD2001DGSR Datasheet(PDF) 39 Page - Texas Instruments