PL460 datasheet(36/48 Pages) MICROCHIP

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PL460

Electrical Characteristics

Data Sheet

DS60001666D - 36

11.4. DC Characteristics

Table 11-5. PL460 DC Characteristics

Parameter

Condition

Symbol

Rating

Unit

Min.

Typ.

Max.

Supply voltage

VDDIO

3.00

3.30

3.60

H-level input voltage (3.3V CMOS)

VIH

2.0

—

VDDIO +0.3

L-level input voltage (3.3V CMOS)

VIL

-0.3

—

0.8

H-level output voltage

3.3V I/O IOH = -100 µA

VOH

VDDIO -0.2

—

VDDIO

L-level output voltage

3.3V I/O IOL = 100 µA

VOL

—

0.2

Internal pull-up resistor(1)

3.3V I/O

Rpu

100

140

kΩ

Internal pull-down resistor(1)

3.3V I/O

Rpd

100

140

Note:

1. Only applicable to pins with internal pulling.

11.5. Power Consumption

The table below provides power consumption of the system (digital and analog) when it is used with

typical AMR protocols. However, it is important to remember that different protocols, or even the

same protocols used with different clock schemes or with different software implementations, can

lead to other consumption figures.

Table 11-6. Full System Power Consumption

Frequency Band

Application Case

Rating

Unit

3V3

12V

Typ.(1)

CENELEC-A

CENELEC-B

Reception waiting for preamble detection

0.6

Reception processing incoming frames

0.6

Transmission with internal driver

104

FCC

Reception waiting for preamble detection

0.6

Reception processing incoming frames

0.6

Transmission with internal driver

166

Notes:

1. TAMB = 25ºC, VDDIO = 3.3V, VDDIN = 3.3V, and VDDIN_AN = 3.3V, G3-PLC.

The table below provides power consumption of the analog IPs in the system. Analog parts are the

PLL used for internal clock generation (supplied from the VDDPLL pin) and the conversion module

composed of the Programmable Gain Amplifier (PGA) and the Analog-to-Digital Converter (ADC),

both supplied from the VDDIN_AN pins.

Take maximum consumption cases into account for supply filter calculation. The supply voltage

drop after the filters must be small enough to ensure the correct operation of the analog IPs. The

voltage applied to VDDPLL and VDDIN_AN must always be greater than Vtypical-10%, VDDPLL >

1.08V, and VDDIN_AN > 3.0V.

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