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DI035P04PT Datasheet(PDF) 2 Page - Diotec Semiconductor

Part # DI035P04PT
Description  P-Channel Power MOSFET
PDF  5 Pages
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Manufacturer  DIOTEC [Diotec Semiconductor]
Direct Link  http://www.diotec.com
Logo DIOTEC - Diotec Semiconductor

DI035P04PT Datasheet(HTML) 2 Page - Diotec Semiconductor

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DI035P04PT
Characteristics (static)
Kennwerte (statisch)
Tj = 25°C
Min.
Typ.
Max.
Drain-Source breakdown voltage – Drain-Source-Durchbruchspannung
- ID = 250 µA
- VGS = 0 V (short)
- V(BR)DSS
40 V
–
–
Drain-Source leakage current – Drain-Source Leckstrom
VDS = 32 V
- VGS = 0 V (short)
- IDSS
–
–
1 µA
Gate-Body leakage current – Gate-Substrat Leckstrom
VGS = ±20 V
- VDS = 0 V (short)
IGSS
–
–
± 100 nA
Gate-Source threshold voltage – Gate-Source Schwellspannung
VGS = VDS
- ID = 250 µA
- VGS(th)
1.2 V
–
2.5 V
Drain-Source on-state resistance – Drain-Source Einschaltwiderstand
- VGS = 10 V
- ID = 10 A
- VGS = 4.5 V
- ID = 8 A
RDS(on)
–
15 mΩ
–
19 mΩ
29 mΩ
Characteristics (dynamic)
Kennwerte (dynamisch)
Tj = 25°C
Min.
Typ.
Max.
Forward Transconductance – Übertragungssteilheit
- VDS = 5 V
- ID = 5 A
gFS
–
15 S
–
Input Capacitance – Eingangskapazität
- VDS = 20 V
VGS = 0 V
f = 1 MHz
Ciss
–
2570 pF
–
Output Capacitance – Ausgangskapazität
- VDS = 20 V
VGS = 0 V
f = 1 MHz
Coss
–
175 pF
–
Reverse Transfer Capacitance – Rückwirkungskapazität
- VDS = 20 V
VGS = 0 V
f = 1 MHz
Crss
–
110 pF
–
Turn-On Delay & Rise Time – Einschaltverzögerung und Anstiegszeit
- VDD = 20 V - ID = 10 A - VGS = 10 V
RG = 3.3 Ω
(Fig. 1)
td(on)
tr
–
14 ns
26 ns
–
Turn-Off Delay & Fall Time – Ausschaltverzögerung und Abfallzeit
- VDD = 20 V - ID = 10 A - VGS = 0 V
RG = 3.3 Ω
(Fig. 1)
td(off)
tf
–
27 ns
5 ns
–
Total Gate Charge – Gesamte Gate-Ladung
- VDD = 20 V - ID = 10 A - VGS = 10 V
Qg
–
30 nC
–
Gate-Source Charge – Gate-Source-Ladung
- VDD = 20 V - ID = 10 A - VGS = 10 V
Qgs
–
4.5 nC
–
Gate-Drain Charge – Gate-Drain-Ladung
- VDD = 20 V - ID = 10 A - VGS = 10 V
Qgd
–
9.5 nC
–
Intrinsic Gate resistance – Innerer Gatewiderstand
f = 1 Mhz
D open
RGi
–
5.1 Ω
–
2
http://www.diotec.com/
©
t
d(on)
V
GS
90%
10%
V
DS
t
r
t
d(off)
t
f
Fig. 1
Test circuit for switching
times (R) and avalanche
energy (L)
(“rise“ and “fall“ refer to I )
D
Testaufbau für Schaltzeiten (R)
und Avalanche-Energie (L)
(“rise“ und “fall“ beziehen sich auf I
D)
V
GS
R
G
R
V
DS
V
DD
I
D
L



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