L99CL01XP datasheet(21/60 Pages) STMICROELECTRONICS

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L99CL01XP

SPI interface

Initialization Register

Address:

Base address + 0x00h

Type:

R, R/W

Reset:

0x0001h

Note:

Writing all [0] to this register will generate a SPI fail (stuck @ ‘0’).

Address

MUX2 MUX1 MUX0 SOA3

SOA2

SOA1

SOA0

R/W

Bit 15:12 Address

Bit 11 WD: Watchdog toggle bit (75ms, start with [0] after Reset, toggled with every SPI

access)

Bit 10 NOCLEAR: With this bit set to:

0: every read access clears the read out status bits

1: any reported status from the read and clear flags are not cleared by a read

The clear of the read and clear flags will be re-enabled by writing a [0] to this bit.

Bit 9 READRAM: With this bit set to:

0: the addressed status data register (see Section 3.1.4: SDO (serial data output)) is

sent back via SDO

1: the addressed control data register is sent back via SDO. This is to verify the written

data in the device.

Note:

The read back of the Status Data Registers will be re-enabled by

writing a [0] to this bit.

Bit 8 PWMsync: internal PWM counter reset. Writing a ‘1’ to this Register will reset the

internal PWM counter after valid SPI command and CSN high. This bit is automatically

reset after synchronization.

Bit 7 MUXEN: Enable current sense output and the OUT voltage level comparator

0: CS pin disabled / OUT voltage comparator disabled (default)

1: CS pin enable / OUT voltage comparator enabled (see MUX[2:0]) setting

L99CL01XP Datasheet(PDF) 21 Page - STMicroelectronics