DLPC8455AMD datasheet(39/73 Pages) TI2

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6.3 Feature Description

6.3.1 Input Sources

Table 6-1. Supported Input Source Parameters

INTERFACE

Bits/Pixel Accepted

(Max)

Bits/Pixel Processed

(Max)

Source Resolution: 2D

Source Resolution: 3D (per Eye) (2)

Min

Max (1)

Max

V-by-One

1280 × 720 (3)

3840 × 2160

1920 × 1080 (FS)

FPD Link

960 × 540

1920 × 1080

1920 × 1080 (FS)

(1)

Despite a wider input range, the output resolution will be limited to the DMD and controller capabilities. The resolutions should be

checked across devices, including with 3D sources.

(2)

FS = Frame Sequential (Full Resolution)

(3)

The minimum clock rate and link rate for the V-by-One interface, as well as Byte Mode, limits the smallest resolution that can be

supported by this interface. This interface supports 3-Byte, 4-Byte, and 5-Byte Modes.

6.3.2 V-by-One Interface

The controller supports a single 8-lane V-by-One port, which can be configured for 1-, 2-, 4-, or 8-lane use. This

interface supports limited lane remapping, which is shown in Table 6-2. Intralane remapping (that is, swapping P

with N) is not supported.

Table 6-2. V-by-One Interface Lane Remapping Options

V-BY-ONE PORT PHYSICAL LANES(1)

CONFIGURATIO

N(2)

# of LANES

LANE 7

LANE 6

LANE 5

LANE 4

LANE 3

LANE 2

LANE 1 LANE 0

—

(1)

The lane numbers in the table header indicate the actual physical lanes defined in the controller interface. The lane numbers listed

below the header are the lane bit numbers transmitted over that physical interface.

(2)

There are two controller lane mapping options, with the option to use fewer than the full eight lanes for each.

Independent of the remapping of the physical V-by-One interface, the support a number of data mappings onto

the actual physical interface as specified by the standard. V-by-One sources must match at least one of the

mappings in Table 6-3, Table 6-4, Table 6-5, Table 6-6, Table 6-7, and Table 6-8.

Table 6-3. V-by-One Data Mapping for 36bpp/30bpp RGB/YCbCr 4:4:4

V-BY-ONE DATA MAP MODE 0

V-BY-ONE INPUT DATA BIT

36bpp RGB/YCbCr 4:4:4(1)

30bpp RGB/YCbCr 4:4:4

MAPPER OUTPUT

D[0]

R/Cr[4]

R/Cr[2]

B(2)

D[1]

R/Cr[5]

R/Cr[3]

B(3)

D[2]

R/Cr[6]

R/Cr[4]

B(4)

D[3]

R/Cr[7]

R/Cr(5]

B(5)

D[4]

R/Cr[8]

R/Cr[6]

B(6)

D[5]

R/Cr[9]

R/Cr[7]

B(7)

D[6]

R/Cr[10]

R/Cr[8]

B(8)

D[7]

R/Cr[11]

R/Cr[9]

B(9)

D[8]

G/Y[4]

G/Y[2]

A(2)

D[9]

G/Y[5]

G/Y[3]

A(3)

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DLPC8445, DLPC8445V, DLPC8455

DLPS253B – SEPTEMBER 2024 – REVISED AUGUST 2025

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