DLPC8445VAMD datasheet(29/73 Pages) TI2

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5.13 V-by-One Interface General Timing Requirements

PARAMETER(1)

MIN

MAX

UNIT

fclock

Source clock frequency

1 lane to 8 lanes

600

MHz

flink-clk

Link clock frequency per lane

8 lanes

MHz

4 lanes

MHz

2 lanes

MHz

1 lane

MHz

flink

Link transfer rate

3-Byte Mode

2.55

Gbps

4 Byte Mode

Gbps

5 Byte Mode

Gbps

tRBIT

Unit Interval

3-Byte Mode

392

500

4 Byte Mode

294

500

5 Byte Mode

294

500

Jitter Margin(2)

0.25

Rise / Fall Time(2)

0.05

tEYE

Differential Data Eye(2)

0.5

tskew_intra

Allowable Intrapair skew

0.3

tskew_inter

Allowable Interpair Skew

Total jitter

0.5

Random jitter

1012 UI

0.2

Dj_ISI

Deterministic jitter (ISI)

0.2

Sinusoidal jitter

0.1

(1)

V-by-One high-speed technology supports 1, 2, 4, or 8-lane operation, in addition to 3-byte, 4-byte, and 5-byte transfer modes

(2)

See V-by-One Timing.

Figure 5-8. V-by-One Timing

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DLPC8445, DLPC8445V, DLPC8455

DLPS253B – SEPTEMBER 2024 – REVISED AUGUST 2025

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