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STM32L4R9AI Datasheet(PDF) 29 Page - STMicroelectronics |
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STM32L4R9AI Datasheet(HTML) 29 Page - STMicroelectronics |
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29 / 306 page ![]() Stop 0(5) Range 1 No Off ON LSE LSI BOR, PVD, PVM RTC, IWDG COMPx (x=1,2) DACx (x=1,2) OPAMPx (x=1,2) USARTx (x=1...5)(6) LPUART1(6) I2Cx (x=1...4)(7) LPTIMx (x=1,2) *** All other peripherals are frozen Reset pin, all I/Os BOR, PVD, PVM RTC, IWDG COMPx (x=1..2) USARTx (x=1...5)(6) LPUART1(6) I2Cx (x=1...4)(7) LPTIMx (x=1,2) OTG_FS(8) Range 2 Stop 1 LPR No Off ON LSE LSI BOR, PVD, PVM RTC, IWDG COMPx (x=1,2) DACx (x=1,2) OPAMPx (x=1,2) USARTx (x=1...5)(6) LPUART1(6) I2Cx (x=1...4)(7) LPTIMx (x=1,2) *** All other peripherals are frozen Reset pin, all I/Os BOR, PVD, PVM RTC, IWDG COMPx (x=1..2) USARTx (x=1...5)(6) LPUART1(6) I2Cx (x=1...4)(7) LPTIMx (x=1,2) OTG_FS(8) Table 4. STM32L4R5xx modes overview (continued) Mode Regulator(1) CPU Flash SRAM Clocks DMA & Peripherals(2) Wakeup source |
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