CY3128
Document #: 38-03047 Rev. *A
Page 2 of 8
VHDL and Verilog Compilers
VHDL and Verilog are powerful, industry standard languages
for behavioral design entry and simulation, and are supported
by all major vendors of EDA tools. They allow designers to
learn a single language that is useful for all facets of the design
process.
VHDL and Verilog offer designers the ability to describe de-
signs at many different levels. At the highest level, designs can
be entered as a description of their behavior. This behavioral
description is not tied to any specific target device. As a result,
simulation can be done very early in the design to verify correct
functionality, which significantly speeds the design process.
The Warp syntax for VHDL and Verilog includes support for
intermediate level entry modes such as state tables and Bool-
ean entry. At the lowest level, designs can be described using
gate-level descriptions. Warp Professional gives the designer
the flexibility to intermix all of these entry modes.
In addition, Verilog and VHDL allow you to design hierarchical-
ly, building up entities in terms of other entities. This allows you
to work either “top-down” (designing the highest levels of the
system and its interfaces first, then progressing to greater and
greater detail) or “bottom-up” (designing elementary building
blocks of the system, then combining these to build larger and
larger parts) with equal ease.
Because these languages are IEEE standards, multiple ven-
dors offer tools for design entry and simulation at both high and
low levels and synthesis of designs to different silicon targets.
The use of device-independent behavioral design entry gives
users the freedom to easily migrate to high volume technolo-
gies. The wide availability of VHDL and Verilog tools provides
complete vendor independence as well. Designers can begin
their project using Warp Professional for Cypress CPLDs and
convert to high volume ASICs using the same VHDL or Ver-
ilog behavioral description with industry-standard synthesis
tools.
The VHDL and Verilog languages also allow users to define
their own functions. User-defined functions allow users to ex-
tend the capabilities of the language and build reusable files
of tested routines. VHDL and Verilog provide control over the
timing of events or processes. They have constructs that iden-
tify processes as either sequential, concurrent, or a combina-
tion of both. This is essential when describing the interaction
of complex state machines.
VHDL and Verilog are rich programming languages. Their flex-
ibility reflects the nature of modern digital systems and allows
designers to create accurate models of digital designs. Be-
cause they are not verbose languages they are easy to learn
and compile. In addition, models created in VHDL and Verilog
can readily be transported to other EDA Environments. Warp
Professional supports IEEE 1076/1164 VHDL including
loops, for/generate statements, full hierarchical designs with
packages, enumerated types, and integers as well as IEEE
1364 Verilog including loops, reduction and conditional op-
erators.
A VHDL Design Example
Design Entry
Warp Professional descriptions specify:
• The behavior or structure of a design, and
• The mapping of signals in a design to the pins of a
PLD/CPLD (optional)
The part of a Warp Professional description that specifies the
behavior or structure of the design is called an entity/archi-
tecture pair. Entity/architecture pairs, as their name implies,
are divided into two parts: an entity declaration, which de-
clares the design’s interface signals (i.e., defines what ex-
ternal signals the design has, and what their directions and
types are), and a design architecture, which describes the
design’s behavior or structure.
The entity portion of a design file is a declaration of what a
design presents to the outside world (the interface). For each
external signal, the entity declaration specifies a signal name,
a direction and a data type. In addition, the entity declaration
specifies a name by which the entity can be referenced in a
design architecture. This section shows code segments from
five sample design files. The top portion of each example
features the entity declaration.
Behavioral Description
The architecture portion of a design file specifies the function
of the design. As shown in Figure 1, multiple design-entry
methods are supported in Warp Professional. A behavioral
description in VHDL often includes well known constructs
such as If...Then...Else, and Case statements. Here is a
code segment from a simple state machine design (soda
vending machine) that uses behavioral VHDL to implement
the design:
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY drink IS
PORT (nickel,dime,quarter,clock:#in
Figure 1. Warp® Design Flow
State Machine
VHDL and
Programming
Timing
Simulator
VHDL, Verilog
&Third-Party
Simulation Models
UltraGen™
Synthesis
and
Fitting
Graphical
File
Verilog Text
HDL Blocks
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