CY3128
Document #: 38-03047 Rev. *A
Page 5 of 8
design files. The top portion of each example features the
module declaration.
Behavioral Description
The module portion of a design file specifies the function of the
design. As shown in Figure 1, multiple design-entry methods
are supported in Warp Professional. A behavioral descrip-
tion in Verilog often includes well known constructs such as
If
…Else, and Case statements. Here is a code segment
from a simple state machine design (soda vending ma-
chine) that uses behavioral Verilog to implement the de-
sign:
MODULE drink (nickel, dime, quarter, clock,
returnDime, returnNickel,
giveDrink);
INPUT nickel, dime, quarter, clock;
OUTPUT returnDime,returnNickel,giveDrink;
REG returnDime, returnNickel, giveDrink;
PARAMETER zero = 0, five = 1, ten = 2,
fifteen = 3, twenty = 4, twentyfive = 5
owedime = 6;
REG[1:0] drinkStatus;
ALWAYS@ (POSEDGE clock)
BEGIN
giveDrink = 0;
returnDime = 0;
returnNickel = 0;
CASE(drinkStatus)
zero: BEGIN
IF (nickel)
drinkStatus = five;
ELSE IF (dime)
drinkStatus = ten;
ELSE IF (quarter)
drinkStatus = twentyfive;
END
five: BEGIN
IF (nickel)
drinkStatus = ten;
ELSE IF (dime)
drinkStatus = fifteen;
ELSE IF (quarter)
BEGIN
drinkStatus = zero;
giveDrink = 1;
END
END
// Several states are omitted in this
// example. The omitted states are ten
// fifteen, twenty, and twentyfive.
owedime: BEGIN
returnDime = 1;
drinkStatus = zero;
END
default: BEGIN
// This makes sure that the state
// machine resets itself if
// it somehow gets into an undefined state.
drinkStatus = zero;
END
ENDCASE
END
ENDMODULE
Verilog is not a strongly typed language. The simplicity and
readability of the following code is increased by use of the
CASEX. The CASEX command accepts “Don’t Cares” and
chooses the branch depending on the value of the expression.
MODULE sequence (clk, s);
INPUT clk;
INOUT s;
WIRE s;
REG temp;
REG[3:0] count;
ALWAYS@(POSEDGE clk)
CASEX(count)
4’b00XX: BEGIN
temp=1;
count=count+1;
end
4’b01XX: BEGIN
temp=0;
count=count+1;
end
4’b100X: BEGIN
temp=1;
count=count+1;
end
default: BEGIN
temp=0;
count=0;
end
ENDCASE
ASSIGN s=temp;
ENDMODULE
Boolean Equations
A second design-entry method available to Warp Professional
users is Boolean equations. Figure 4 displays a schematic of a sim-
ple one-bit half adder. The following code describes how this one-bit
half adder can be implemented in Warp Professional with Boolean
equations:
MODULE half_adder(x, y, sum, carry);
INPUT x, y;
OUTPUT sum, carry;
Figure 4. One-Bit Half Adder
x
y
Carry
Sum
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