CY3128
Document #: 38-03047 Rev. *A
Page 7 of 8
© Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
tive waveform viewing as well as graphical creation and editing
of stimulus waveforms. The simulator also provides the ability
to probe internal nodes, and automatically generate clocks
and pulses. The version in Warp Professional has the ability
to compare waveforms and highlight differences before and
after a design change. In Warp Professional there is a maxi-
mum simulation time of 5 ms. Source-level simulation support
and unlimited timing simulation are available with Warp Enter-
prise (CY3130 and CY3138).
No matter what HDL you use for design entry, Warp Profes-
sional automatically creates a VHDL netlist to enable the use
of the timing simulator. However, Warp Professional can gen-
erate both VHDL and Verilog timing models for third-party
simulators to perform functional and timing verifications of the
synthesized design.
Architecture Explorer™
The Architecture Explorer graphically displays how the design
will be implemented on the chip. It provides a view of the entire
device to show what memory elements and logic clusters have
been used for what part of the design. This display gives the
designer an idea of what resources are free. The Architecture
Explorer allows you to zoom in multiple times. At maximum
zoom it displays the logic gate implementation in each macro-
cell. The Architecture Explorer is available for PSI, Delta39K,
and Quantum38K devices.
Timing Analyzer
The timing analyzer gives the time across any path as well as
the breakdown of what steps are causing the timing delays.
This tool does not simply display the general specification for
the target device but a worst-case simulation of the actual path
being taken through the device. When you highlight a path on
the timing analyzer, the source and destination of that path are
displayed on the Architecture Explorer. The timing analyzer
graphical interface is available for PSI, Delta39K, and
Quantum38K devices. However, for other devices the same
information is available in a report file.
Programming
Cypress’s FLASH370i, Ultra37000, Quantum38K, Delta39K,
and PSI In-System Reprogrammable™ (ISR™) devices can
be programmed on board with an ISR programmer. For PSI,
Delta39K and Quantum38K CPLDs Warp Professional pro-
duces an Intel hex file. The ISR programmer converts this file
into STAPL and programs the device. For Ultra37000 and
FLASH370i devices, Warp Professional produces a JEDEC file.
For Ultra37000, the ISR programmer converts this file into
JAM/STAPL and programs the device. For FLASH370i, the JE-
DEC file is used directly to program the device.
Warp Professional comes with an UltraISR Programming Ca-
ble and a Delta39K\Ultra37000 prototype board with a
CY37256V 160-pin TQFP device and a CY39100V 208-pin
PQFP device.[1]
The JEDEC and Intel hex files produced by Warp Professional
can also be used with any qualified third party programmer to
program Cypress CPLDs.
For more information on Cypress’s ISR software see the ISR
Programming Kit (CY3900i) data sheet.
Warp® Software System Requirements
• IBM PC or equivalent (Pentium® class recommended)
• 32 MB of RAM (64 MB recommended)
• 110 MB Disk Space
• CD-ROM drive
• Windows 98, or Windows NT 4.0
• Warp Professional Hardware Key for License
ISR Software PC Requirements
• IBM PC or compatible running Windows 98, Windows 98
Second Edition, Windows ME, Windows NT 4.0 Service
Pack 5 or later, or Windows 2000 Service Pack 1 or later
• One free parallel port
• Minimum of 32 MB of RAM
• Approximately 30 MB free hard disk space
Product Ordering Information
Warp Professional includes:
• Cypress Lab CD-ROM with Warp Professional, ISR soft-
ware, on-line documentation (Getting Started Manual, Us-
er’s Guide, HDL Reference Manual, Databook) and other
Cypress software
• VHDL for Programmable Logic Textbook
• UltraISR Programming Cable
• Delta39K\Ultra37000 prototype board with a CY37256V
160-pin TQFP device and a CY39100V 208-pin PQFP de-
vice[1]
• Registration Card
• Hardware License Key
Warp Professional, Warp Enterprise, UltraGen, Ultra37000, Quantum38K, Delta39K, PSI, Programmable Serial Interface,
MAX340, ISR, In-System Reprogrammable, and FLASH370i are trademarks of Cypress Semiconductor Corporation.
Warp is a registered trademark of Cypress Semiconductor Corporation.
Pentium is a registered trademark of Intel Corporation.
Windows 98, Windows 2000 and Windows NT are trademarks of Microsoft Corporation.
Solaris is a trademark of Sun Microsystems Corporation.
Active-HDL is a trademark of Aldec Incorporated.
Product Code
Description
CY3128R62
Warp Professional CPLD software for PCs
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
