CY3128
Document #: 38-03047 Rev. *A
Page 6 of 8
ASSIGN sum = x^y;
ASSIGN carry = x&y;
ENDMODULE
Structural Verilog
While all of the design methodologies described thus far are
high-level entry methods, structural Verilog provides a method
for designing at a very low level. In structural descriptions, the
designer simply lists the components that make up the design
and specifies how the components are wired together.
Figure 5 displays the schematic of a simple 3-bit shift register and
the following code shows how this design can be described in
Warp Professional using structural Verilog.
MODULE shifter3 (clk, x, q0, q1, q2);
INPUT clk, x;
OUTPUT q0, q1, q2;
WIRE q0, q1, q2;
REG q0_temp, q1_temp, q2_temp;
DFF d1(x,clk,q0_temp);
DFF d2(q0_temp,clk,q1_temp);
DFF d3(q1_temp,clk,q2_temp);
ASSIGN q0 = q0_temp;
ASSIGN q1 = q1_temp;
ASSIGN q2 = q2_temp;
ENDMODULE;
All of the design-entry methods described can be mixed as
desired so long as only one HDL is used. VHDL and Verilog
have the ability to combine both high- and low-level entry
methods in a single file. The flexibility and power of VHDL and
Verilog allow users of Warp Professional to describe designs
using whatever method is appropriate for their particular design.
Finite State Machine Editor
Aldec’s Active-HDL FSM finite state machine editor, allows
graphic design entry through the use of graphical state dia-
grams. A design may be represented graphically using state
diagrams and data flow logic. This tool will automatically
generate the HDL code of the design.
HDL Block Diagram Editor
The HDL block diagram editor lets you represent portions of
your code with graphical symbols. This representation allows
you to view the high-level structure of your complex designs
and lets you copy and paste entire modules of your design
within or between designs. The editor comes with a library of
HDL blocks optimized for Cypress devices. Warp Enterprise™
(CY3130 and CY3138) comes with a utility that converts HDL
text into these blocks.
Language Assistant
The language assistant is a library of language templates that
you can browse and automatically insert into your HDL text.
They provide syntax and structure and give examples to aid
users who are new to using a particular HDL.
Flow Manager
The flow manager is a special interface that helps you keep
track of your complex projects. It arranges the tools as part of
the logical flow the designer takes through a project and re-
members what steps have been completed on which designs.
Compilation
Once the VHDL or Verilog description of the design is com-
plete, it is compiled using Warp Professional. Although imple-
mentation is with a single command, compilation is actually a mul-
tistep process as shown in Figure 1. The first part of the compilation
process is the same for all devices. The input description is synthe-
sized to a logical representation of the design. Warp synthesis is
unique in that the input languages support device-independent de-
sign descriptions. Competing programmable logic compilers re-
quire very specific and device-dependent information in the design
description.
Warp synthesis is based on UltraGen technology. This tech-
nology allows Warp Professional to infer adders, subtractors,
multipliers, comparators, counters and shifters from the be-
havioral descriptions. Warp Professional then replaces these
operators internally with an architecture-specific circuit. This
circuit or “module” is also pre-optimized for either area or
speed. Warp Professional uses the appropriate implementa-
tion based on user directives.
The second step of compilation is an iterative process of opti-
mizing the design and fitting the logic into the targeted device.
Logical optimization in Warp Professional is accomplished using
Espresso algorithms. The optimized design is automatically fed to
the Warp Professional fitter for targeting a PLD or CPLD. This fitter
supports the automatic or manual placement of pin assignments as
well as automatic selection of D or T flip-flops. After optimization and
fitting, Warp Professional creates a JEDEC or Intel hex file for the
specified PLD or CPLD.
Automatic Error Tracking
Warp Professional features automatic error location that al-
lows problems to be diagnosed and corrected in seconds. Er-
rors from compilation are displayed immediately in a window.
If the user highlights a particular error, Warp Professional will
automatically open the source code file and highlight the of-
fending line in the entered design. If the device fitting process
includes errors, a window will again describe them. A detailed
report file is generated indicating the resources required to fit
the input design and any problems that occurred in the pro-
cess.
Timing Simulation
Warp Professional includes a post-synthesis timing simulator
called Active-HDL Sim. Active-HDL Sim features a graphical
waveform simulator that can be used to simulate PLD/CPLD
designs generated in Warp Professional. The simulator pro-
vides timing simulation for PLDs/CPLDs and features interac-
Figure 5. Three-Bit Shift Register Circuit Design
clk
dq
clk
d
q
clk
dq
x
clk
q0
q1
q2
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