SST26WF080BA datasheet(84/96 Pages) MICROCHIP

84 / 96 page

SST26WF040B/040BA SST26WF080B/080BA

DS20005283C-page 84

 2014-2017 Microchip Technology Inc.

65H

A14:A8

A9H

Exit Deep Power-down to next operation delay –10 µs

Delay = (count +1)*unit

A12:A8 = count = 9 = 01001b

A14:A13 units = 01b = 1µs

A15

Exit Power-down Instruction– ABH = 10101011b

A15=1b

66H

A22:A16

D5H

A22:A16=1010101b

A23

Enter Power-down instruction – B9H = 10111001b

A23 = 1b

67H

A30:A24

5CH

A30:A24 = 1011100

A31

Deep Power-down Supported

0:supported

1:not supported

JEDEC Flash Parameter Table: 15th DWORD

68H

A3:A0

29H

4-4-4 mode disable sequences

Xxx1b: issue FF instruction

1xxxb: issue the Soft Reset 66/99 sequence.

A7:A4

4-4-4 mode enable sequences

X_xx1xb: issue instruction 38h

69H

C2H

4-4-4 mode enable sequences

A8 = 0

0-4-4 mode supported

0:not supported

1:supported

A15:A10

0-4-4 Mode Exit Method

X1_xxxx:Mode Bit[7:0] Not= AXh

1x_xxxx Reserved = 1

6AH

A19:A16

5CH

0-4-4 Mode Entry Method

X1xxb: M[7:0]=AXh

1xxxb:Reserved =1

A22:A20

Quad Enable Requirements (QER)

101b: Quad Enable is bit 1 of the configuration register.

A23

HOLD and Reset Disable

0:feature is not supported

6BH

A31:A24

FFH

Reserved bits = 0xFF

JEDEC Flash Parameter Table: 16th DWORD

A6:A0

F0H

Volatile or Non-Volatile Register and Write Enable Instructions for

Status Register 1

Xx1_xxxxb:Status Register 1 contains a mix of volatile and non-volatile

bits. The 06h instruction is used to enable writing to the register.

X1x_xxxxb: Reserved = 1

1xx_xxxxb: Reserved = 1

Reserved =1b

A13:A8

30H

Soft Reset and Rescue Sequence Support

X1_xxxxb: reset enable instruction 66h is issued followed by reset

instruction 99h.

1x_xxxxb: exit 0-4-4 mode is required prior to other reset sequences.

A15:A14

Exit 4-Byte Addressing

Not supported

TABLE 11-2:

SERIAL FLASH DISCOVERABLE PARAMETER (SFDP) SST26WF080B/080BA

(CONTINUED) (9 OF 16)

Address

Bit Address

Data

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