MPFS160T datasheet(40/50 Pages) MICROCHIP

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Low Power

PolarFire SoC FPGAs offer a variety of techniques and capabilities to lower the total application power. Users can

take advantage of these features to lower both capital and operational expenditures with smaller or no heat sinks,

smaller or fewer fans, lower cooling costs, and so on. Additionally, the lower total power advantage can also allow the

user to pack more compute operations into an existing thermal budget.

6.1

Non-Volatile Technology

Using a non-volatile complementary metal–oxide semiconductor (CMOS) technology for the FPGA configuration cells

offers several power advantages over SRAM FPGA technology.

• A non-volatile switch uses lower power than a SRAM switch, leading to lower static power consumption.

• The FPGA fabric retains the configurations at power down.

• No SRAM configuration in-rush currents

• No external configuration component is needed

6.2

Lower Power "L" Devices

Low power (L) devices provide up to 35 percent lower static power with identical electrical specifications to the STD

speed grade device. L devices can be ordered as described in the section Ordering Information.

6.3

Low-Power Transceiver Lane

PolarFire SoC FPGAs’ low-power capability is also extended to the industry’s most power efficient transceiver lane,

enabling 10GBASE-KR applications at less than 100 mW of power per lane. The transceiver lane has comprehensive

power-down controls to optimize power consumption, including programmable amplitude and edge rate control.

The following illustration shows the connection between transceiver power and data rate.

Figure 6-1. Transceiver Power versus Data Rate

Low Power

and its subsidiaries

Overview

DS60001656C-page 40

MPFS160T Datasheet(PDF) 40 Page - Microchip Technology