ADIN1300CCPZ-R7 datasheet(13/79 Pages) AD

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Data Sheet

ADIN1300

Rev. 0 | Page 13 of 79

Pin No.

Mnemonic

Description

GP_CLK/RX_ER/

MDIX_MODE1

General-Purpose Output on which PHY Clocks can be Made Available (GP_CLK).

RMII/MII Mode Receive Error Detected Output (RX_ER). When asserted high, it

indicates that the PHY has detected a receive error.

4-Level Hardware Configuration Pin for Auto-MDIX Configuration (MDIX_MODE). See

Table 24.

Power and Ground

Pins

4, 28, 36

DVDD_0P9

0.9 V Digital Core Power Supply Input. Connect 0.1 μF and 0.01 μF capacitors to GND

as close as possible to these pins.

GND

This pin must be connected to GND on the board.

11, 20

AVDD_3P3

3.3 V Power Supply Input for the PHY Interface, Analog Circuitry, Crystal Oscillator, DLL,

RESET_N, CLK25_REF Generation, and LED Circuitry. Connect 0.1 μF and 0.01 μF

capacitors to GND as close as possible to these pins.

25, 31, 40

VDDIO

3.3 V/2.5 V/1.8 V MDIO and MAC Interface Power Supply Input. Connect 0.1 μF and

0.01 μF capacitors to GND as close as possible to these pins. If using 3.3 V, to minimize

power supplies, VDDIO and AVDD_3P3 can be connected to the same supply.

Exposed Pad. The LFCSP package has an exposed pad that must be soldered to a

metal plate on the PCB for mechanical reasons and to GND. A 4 × 4 array of thermal

vias beneath the exposed GND pad is also required.

1 In cases where a pin is shared between a functional signal(s) and a hardware pin configuration signal(s), the hardware pin configuration signal(s) is the last name in the

mnenomic and the pin is referred to using the functional signal(s) name throughout the data sheet.

Table 14. Pin Function Descriptions For Each MAC Interface Option

Pin No.

Mnemonic1

MAC Interface Pin Function2

RGMII

MII and EEE Advertisement Disabled3

MII and EEE Advertisement Enabled3,4

RMII

TXD_1

TXD_2

TXD_3

XTAL_I/CLK_IN/REF_CLK

REF_CLK5

LED_06/COL/TX_ER

COL

TX_ER7

INT_N6/CRS

CRS

GP_CLK6/RX_ER

RX_ER

RXD_3

RXD_2

RXD_1

RXD_0

RXC/RX_CLK

RXC

RX_CLK

RX_CTL/RX_DV/CRS_DV

RX_CTL

RX_DV

CRS_DV

TX_CTL/TX_EN

TX_CTL

TX_EN

TXC/TX_CLK

TXC

TX_CLK

TXD_0

1 Hardware pin configuration signal(s) have been omitted for clarity.

2 Wherever the field is left blank, the pin function is the first function listed in the Mnemonic column.

3 EEE advertisement enabled/disabled using the hardware pin configuration. See the Hardware Configuration Pins section.

4 EEE does not support half duplex. Therefore, no CRS pin or COL pin is required.

5 A 50 MHz reference clock must be supplied on the XTAL_I/CLK_IN/REF_CLK pin when using the RMII MAC interface option.

6 These pin functions can also be reconfigured via software.

7 Because TX_ER shares a pin with COL, this pin is grouped with the PHY output pins, even though TX_ER is actually a PHY input pin.

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