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ADIN1300

Data Sheet

Rev. 0 | Page 46 of 79

Bits

Bit Name

Description

Reset

Access

NP_TOGGLE

Toggle (T) is used by the arbitration function to ensure synchronization with the link partner

during next page exchange. This bit always takes the opposite value of the toggle bit in the

previously exchanged link code word.

0x0

[10:0]

NP_CODE

Message code field is an 11-bit wide field, encoding 2048 possible messages. If the message

page bit is set to Logic 0, the bit encoding of the link code word is interpreted as an

unformatted page.

0x1

R/W

Autonegotiation Link Partner Received Next Page Register

Address: 0x0008, Reset: 0x0000, Name: LP_RX_NEXT_PAGE

This address corresponds to the autonegotiation link partner received next page register specified in Clause 28.2.4.1.7 of IEEE Standard 802.3.

Table 39. Bit Descriptions for LP_RX_NEXT_PAGE

Bits

Bit Name

Description

Reset

Access

LP_NP_NEXT_PAGE

Link partner next page (NP) is used by the next page function to indicate that the link

partner sends additional next page(s). Otherwise, this is the last next page to be transmitted.

0x0

LP_NP_ACK

This bit is used by the internal handshaking in autonegotiation and must be ignored.

0x0

1: link partner has successfully received its link code word.

0: link partner has not received its link code word.

LP_NP_MSG_PAGE

Link partner message page (MP) is used by the next page function to indicate that this is

a message page. Otherwise, this is an unformatted page.

0x0

LP_NP_ACK_2

Acknowledge 2 (Ack2) is used by the next page function to indicate that the link partner

has the ability to comply with the message.

0x0

LP_NP_TOGGLE

Link partner toggle (T) is used by the arbitration function to ensure synchronization with

the link partner during the next page exchange. This bit always takes the opposite value

of the toggle bit in the previously exchanged link code word.

0x0

[10:0]

LP_NP_CODE

Link partner message code field is an 11-bit wide field, encoding 2048 possible

messages. If the message page bit is set to Logic 0, the bit encoding of the link code

word is interpreted as an unformatted page.

0x0

Master Slave Control Register

Address: 0x0009, Reset: 0x0200, Name: MSTR_SLV_CONTROL

This address corresponds to the master slave control register specified in Clause 40.5.1.1 of IEEE Standard 802.3. Note that the default

reset value of this register is dependent on the hardware configuration pins settings.

Table 40. Bit Descriptions for MSTR_SLV_CONTROL

Bits

Bit Name

Description

Reset

Access

[15:13]

TST_MODE

Transmitter test mode operations are defined by the test mode bits as specified

in Clause 40.6.1.1.2 of IEEE Standard 802.3.

0x0

R/W

111: reserved.

110: reserved.

101: reserved.

100: Test Mode 4—transmitter distortion test.

011: Test Mode 3—transmit jitter test in slave mode.

010: Test Mode 2—transmit jitter test in master mode.

001: Test Mode 1—transmit waveform test.

000: normal operation.

MAN_MSTR_SLV_EN_ADV

Manual Master/Slave Enable Advertisement Bit.

0x0

R/W

1: enable master slave manual configuration value.

0: disable master slave manual configuration value.

MAN_MSTR_ADV

Master/Slave Advertisement Bit.

0x0

R/W

1: configure PHY as master during master slave negotiation only when

MAN_MSTR_SLV_EN_ADV is set to Logical 1.

0: configure PHY as slave during master slave negotiation only when

MAN_MSTR_SLV_EN_ADV is set to Logical 1.

ADIN1300CCPZ-R7 Datasheet(PDF) 46 Page - Analog Devices

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