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ADIN1300CCPZ-R7 Datasheet(PDF) 39 Page - Analog Devices |
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ADIN1300CCPZ-R7 Datasheet(HTML) 39 Page - Analog Devices |
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39 / 79 page  Data Sheet ADIN1300 Rev. 0 | Page 39 of 79 REGISTER SUMMARY The MII management interface provides a 2-wire serial interface between a host processor or MAC and the ADIN1300 allowing access to control and status information in the subsystem and PHY core management registers. The interface is compatible with both IEEE Standard 802.3 Clause 22 and Clause 45 management frame structures. The device supplements the registers specified in IEEE Standard 802.3 with an additional set of registers that are accessed indirectly. These registers are referred to as extended management interface (EMI) registers. The EMI registers can be accessed using the interface specified under Clause 45. However, for systems that do not support this interface, an alternative access mechanism is provided using the interface specified under Clause 22. The PHY Core Register Summary section and the Subsystem Register Summary section list the PHY core and subsystem registers. PHY CORE REGISTER SUMMARY The PHY core registers are made up of the following three register groupings: • 0x0000 to 0x000F, IEEE standard registers • 0x0010 to 0x001F, vendor specific registers • PHY core EMI registers at Device Address 0x1E The IEEE standard registers and vendor specific registers are accessed using Clause 22 access, and the EMI registers are accessed using Clause 45 access. The ADIN1300 supports the IEEE Clause 45 MDIO manageable device (MMD) registers associated with EEE. These registers are all remapped to the Device Address 0x1E, so they are available at the same device address as the rest of the PHY extended management registers. For systems that do not support the interface specified under Clause 45, the EMI registers can be accessed using Clause 22 access via Register 0x0010 and Register 0x0011. The default value of some of the registers are determined by the value of the hardware configuration pins, which are read just after the RESET_N pin is deasserted (see the Hardware Configuration Pins section). This allows the default operation of the ADIN1300 to be configured in unmanaged applications. The default values in Table 30 assume the ADIN1300 is configured as follows: • Auto MDIX, prefer MDI • Autonegotiation enabled • All speeds advertised • EEE, energy detect power-down, and downspeed disabled • ADIN1300 is not configured to enter software power-down after reset • RGMII MAC interface selected with 2 ns internal delay on RXC and TXC Table 30. MDIOMAP_GEPHY Register Summary Address Name Description Reset Access 0x0000 MII_CONTROL MII Control Register. 0x1040 R/W 0x0001 MII_STATUS MII Status Register. 0x7949 R 0x0002 PHY_ID_1 PHY Identifier 1 Register. 0x0283 R 0x0003 PHY_ID_2 PHY Identifier 2 Register. 0xBC30 R 0x0004 AUTONEG_ADV Autonegotiation Advertisement Register. 0x01E1 R/W 0x0005 LP_ABILITY Autonegotiation Link Partner Base Page Ability Register. 0x0000 R 0x0006 AUTONEG_EXP Autonegotiation Expansion Register. 0x0064 R 0x0007 TX_NEXT_PAGE Autonegotiation Next Page Transmit Register. 0x2001 R/W 0x0008 LP_RX_NEXT_PAGE Autonegotiation Link Partner Received Next Page Register. 0x0000 R 0x0009 MSTR_SLV_CONTROL Master Slave Control Register. 0x0200 R/W 0x000A MSTR_SLV_STATUS Master Slave Status Register. 0x0000 R 0x000F EXT_STATUS Extended Status Register. 0x3000 R 0x0010 EXT_REG_PTR Extended Register Pointer Register. 0x0000 R/W 0x0011 EXT_REG_DATA Extended Register Data Register. 0x0000 R/W 0x0012 PHY_CTRL_1 PHY Control 1 Register. 0x0002 R/W 0x0013 PHY_CTRL_STATUS_1 PHY Control Status 1 Register. 0x1041 R/W 0x0014 RX_ERR_CNT Receive Error Count Register. 0x0000 R 0x0015 PHY_CTRL_STATUS_2 PHY Control Status 2 Register. 0x0000 R/W 0x0016 PHY_CTRL_2 PHY Control 2 Register. 0x0308 R/W 0x0017 PHY_CTRL_3 PHY Control 3 Register. 0x3048 R/W 0x0018 IRQ_MASK Interrupt Mask Register. 0x0000 R/W 0x0019 IRQ_STATUS Interrupt Status Register. 0x0000 R 0x001A PHY_STATUS_1 PHY Status 1 Register. 0x0300 R 0x001B LED_CTRL_1 LED Control 1 Register. 0x0001 R/W |
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