ADL5566ACPZ-R7 datasheet(16/24 Pages) AD

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ADL5566

Data Sheet

Rev. C | Page 16 of 24

INPUT AND OUTPUT INTERFACING

The ADL5566 can be configured as a differential input to

differential output driver, as shown in Figure 37. The 36 Ω

resistors, R1 and R2, combined with the ETC1-1-13 balun

transformer, provide a 50 Ω input match for the 160 Ω input

impedance. The input and output 0.1 μF capacitors isolate the

VCC/2 bias from the source and balanced load. The load should

equal 200 Ω to provide the expected ac performance (see the

Specifications section).

ETC1-1-13

VCC

½ RL

0.1µF

–

ADL5566

0.1µF

50Ω

Figure 37. Differential Input to Differential Output Configuration

The differential gain of the ADL5566 is dependent on the source

impedance and load, as shown in Figure 38.

5Ω

80Ω

500Ω

80Ω

½ RS

0.1µF

–

ADL5566

Figure 38. Differential Input Loading Circuit

The differential gain can be determined by







500

(1)

Single-Ended Input to Differential Output

The ADL5566 can also be configured in a single-ended input to

differential output driver, as shown in Figure 39. In this

configuration, the gain of the part is reduced due to the application

of the signal to only one side of the amplifier. The input and output

0.1 μF capacitors isolate the VCC/2 bias from the source and the

balanced load. R2 is used to match the single-ended input

impedance of the amplifier (131 Ω) with the 50 Ω source. R1 is

selected to balance the input of the amplifier. See the Application

Note AN-0990 for more information on terminating single-ended

inputs. The performance for this configuration is shown in

Figure 16 and Figure 24.

VCC

½ RL

0.1µF

–

ADL5566

0.1µF

77Ω

30Ω

Figure 39. Single

-Ended Input to Differential Output Configuration

The single-ended gain configuration of the ADL5566 is dependent

on the source impedance and load, as shown in Figure 40.

5Ω

80Ω

500Ω

80Ω

½ RL

0.1µF

–

ADL5566

0.1µF

77Ω

30Ω

Figure 40. Single-Ended Input Loading Circuit

The single-ended gain can be determined by the following two

equations:

131







MATCH

































500

GAIN ADJUSTMENT AND INTERFACING

The effective gain of the ADL5566 can be reduced by adding two

resistors in series with the inputs to reduce the 16 dB gain.

5Ω

80Ω

500Ω

80Ω

½ RS

0.1µF

–

ADL5566

RSERIES

RSHUNT

Figure 41. Gain Adjustment Using a Series Resistor Show

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