CC1020-RTR1 datasheet(47/95 Pages) TI1

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CHP _ CURRENT / 4

CHP

ref

PLL _ BW

174

16 log

7.126

CC1020

www.ti.com

SWRS046H – NOVEMBER 2006 – REVISED MARCH 2015

After calibration the PLL bandwidth is set by the PLL_BW register in combination with the external loop

filter components calculated above. The PLL_BW can be found from Equation 31.

(31)

Where:

fref is the reference frequency (in MHz).

The PLL loop filter bandwidth increases with increasing PLL_BW setting. Note that in SmartRF Studio

PLL_BW is fixed to 9E hex when the channel spacing is set up for 12.5 kHz, optimized selectivity.

After calibration the applied charge pump current (CHP_CURRENT[3:0]) can be read in the STATUS1

(32)

The combined charge pump and phase detector gain (in A/rad) is given by the charge pump current

divided by 2

π.

The PLL bandwidth will limit the maximum modulation frequency and hence, data rate.

5.12.2 VCO and PLL Self-Calibration

To compensate for supply voltage, temperature and process variations, the VCO and PLL must be

calibrated. The calibration is performed automatically and sets the maximum VCO tuning range and

optimum charge pump current for PLL stability. After setting up the device at the operating frequency, the

self-calibration can be initiated by setting the CAL_START bit in the CALIBRATE register. The calibration

result is stored internally in the chip, and is valid as long as power is not turned off. If large supply voltage

drops (typically more than 0.25 V) or temperature variations (typically more than 40°C) occur after

calibration, a new calibration should be performed.

The nominal VCO control voltage is set by the CAL_ITERATE[2:0] bits in the CALIBRATE register.

The CAL_COMPLETE bit in the STATUS register indicates that calibration has finished. The calibration

wait time (CAL_WAIT) is programmable and is inverse proportional to the internal PLL reference

frequency. The highest possible reference frequency should be used to get the minimum calibration time.

It is recommended to use CAL_WAIT[1:0] = 11 in order to get the most accurate loop bandwidth.

Table 5-11. Typical Calibration Times

CALIBRATION

REFERENCE FREQUENCY [MHz]

TIME [ms]

CAL_WAIT

1.8432

7.3728

9.8304

49 ms

12 ms

10 ms

60 ms

15 ms

11 ms

71 ms

18 ms

13 ms

109 ms

27 ms

20 ms

The CAL_COMPLETE bit can also be monitored at the LOCK pin, configured by LOCK_SELECT[3:0] =

0101, and used as an interrupt input to the microcontroller.

To check that the PLL is in lock the user should monitor the LOCK_CONTINUOUS bit in the STATUS

LOCK_SELECT[3:0] = 0010.

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